A Communication Scheme for Defect Tolerant Arrays

  • J. G. Delgado-Frias
  • W. R. Moore


In the past several years, the switching time of logic circuits has markedly decreased (Ko et al., 1983). Consequently, long interconnection paths have become a major concern and in many cases the main factor limiting the speed of processors. This is particularly true in the case of array architectures which exploit parallelism to achieve higher performance but require good, often nearest neighbor, communication between the processors.


Communication Scheme VLSI System Array Architecture Logical Array Link Module 
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Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • J. G. Delgado-Frias
    • 1
  • W. R. Moore
    • 1
    • 2
  1. 1.Dept. of Electrical EngineeringState University of New YorkBinghamtonUSA
  2. 2.Dept. of Engineering ScienceUniversity of OxfordOxfordUK

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