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A Communication Scheme for Defect Tolerant Arrays

  • J. G. Delgado-Frias
  • W. R. Moore

Abstract

In the past several years, the switching time of logic circuits has markedly decreased (Ko et al., 1983). Consequently, long interconnection paths have become a major concern and in many cases the main factor limiting the speed of processors. This is particularly true in the case of array architectures which exploit parallelism to achieve higher performance but require good, often nearest neighbor, communication between the processors.

Keywords

Communication Scheme VLSI System Array Architecture Logical Array Link Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. Delgado-Frias, J.G., Moore, W.R. and Trotter, J.A., 1988, “High Harvest Approaches for 2-D Arrays,” in Yield Modelimg and Defect Tolerance in VLSI, W.R. Moore, W. Maly and A. Strojwas (Eds), Bristol, UK: Adam Hilger, pp. 191–202.Google Scholar
  2. Delgado-Frias, J.G. and Moore, W.R., 1989, “A WSI Architecture for Semantic Networks,” in VLSI for Artificial Intelligence, J.G. Delgado-Frias and W.R. Moore (Eds), Boston: Kluwer Academic Publishers, pp. 144–155.CrossRefGoogle Scholar
  3. Ko, W.C., Peltzer, D.L. and Gaskill, J.R., 1983, “Fast Z: A Simplified Bipolar Technology for VLSI,” in Proceedings on the IEEE University/Government/Industry Microelectronics Symposium, pp. 65-71, College Station, TX.Google Scholar
  4. Koren, I., 1981, “A Reconfigurable and Fault-tolerant Multiprocessor Array,” in Proc. of the 8th Annual Symposium on Computer Architecture, pp. 425-442.Google Scholar
  5. Kung, H.T. and Lam, M.S., 1984, “Wafer-scale Integration and Two-level pipelined Implementations of Systolic Arrays.” J. Parallel and Distributed Computing, vol. 2, pp. 32-63.Google Scholar
  6. Kung, S-Y, Jean, S-N, and Chang, C-W, 1989, “Fault-Tolerant Array Processors Using Single-Track Switches,” IEEE Transactions on Computers, vol. 38, no. 4, pp. 501–513.CrossRefGoogle Scholar
  7. Mead, C. and Rem, M., 1982, “Minimum Propagation Delays in VLSI,” IEEE J. of Solid-State Circuits, vol. SC-17, no. 4, pp. 773–775.CrossRefGoogle Scholar
  8. Mohsen, A.M. and Mead, C.A., 1979, “Delay-Time Optimization for Driving and Sensing of Signals on High-Capacitance Paths of VLSI Systems,” IEEE J. of Solid-State Circuits, vol. SC-14, no. 2, pp. 462–470.CrossRefGoogle Scholar
  9. Moore, W.R., McCabe, A. and Urquhart, It. (Eds), 1987, Systolic Arrays. Bristol, UK: Adam Hilger.zbMATHGoogle Scholar
  10. Negrini, R., Sami, M.G., and Stefanelli, R., 1989, Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays. Cambridge, Mass.: The MIT Press.Google Scholar
  11. Stapper, C.H., Armstrong, F.M., and Saji, K., 1983, “Integrated Circuit Yield Statistics,” Proceedings of the IEEE, vol. 71, no. 4, pp. 453–470.CrossRefGoogle Scholar
  12. Tanenbaum, A.S., 1981, Computer Networks. London: Prentice-Hall.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • J. G. Delgado-Frias
    • 1
  • W. R. Moore
    • 1
    • 2
  1. 1.Dept. of Electrical EngineeringState University of New YorkBinghamtonUSA
  2. 2.Dept. of Engineering ScienceUniversity of OxfordOxfordUK

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