An Efficient Reconfiguration Scheme for WSI of Cube-Connected Cycles with Bounded Channel Width

  • H. Y. Youn
  • A. D. Singh
  • J. H. Kim


Wafer Scale Integration(WSI) technology1 allows us to realize the processor arrays of a certain interconnection topology on a single wafer. The performance improvement of the WSI processor arrays, compared to the uniprocessor system, is expected to be substantial. It was achieved by parallel processing using multiple processors and fast data communication between interacting processors. The off-chip communication delay is generally much bigger than that of on-chip communication. Therefore the performance improvement due to the WSI implementation of processor arrays will be significant for the problems requiring intensive communication between processors.


Channel Width Processor Array Fault Distribution Rectangular Array Target Array 
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  1. [1]
    W.R. Moore, “A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield,” Proc. IEEE, vol. 74, pp.684–698, May 1986.CrossRefGoogle Scholar
  2. [2]
    C.H. Stapper et al., “Integrated Circuit Yield Statistics,” in Proc. IEEE, vol. 71, April 1983.Google Scholar
  3. [3]
    I. Koren and M.A. Breuer, “On area and yield considerations for fault-tolerant VLSI processor arrays,” IEEE Trans. Comput. vol. c-33, pp. 21–27, Jan. 1984.CrossRefGoogle Scholar
  4. [4]
    T. Leighton and C.E. Leiserson, “Wafer-Scale Integration of Systolic Arrays,” IEEE Trans. Comput. vol. c-34, pp. 448–461, May 1985.CrossRefGoogle Scholar
  5. [5]
    A.D. Singh, “Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays,”, in Trans. Comput. vol. c-37, Nov. 1988.Google Scholar
  6. [6]
    H.Y. Youn and A.D. Singh, “On Area Efficient and Fault Tolerant Tree Embedding In VLSI,” in Proc. Int’l Conf. Parallel Processing, pp. 171-178, Aug. 1987.Google Scholar
  7. [7]
    I. Koren, “A Reconfigurable and Fault-tolerant VLSI Multiprocessor Array,” in Proc. 8th Annu. Symp. Comput. Arch., pp. 425-431, May 1981.Google Scholar
  8. [8]
    J.W. Greene and A. El Gamal, “Configuration of VLSI Arrays in the Presence of Defects,” J. ACM, Vol. 31, No. 4, pp. 694–717, 1984.zbMATHCrossRefGoogle Scholar
  9. [9]
    M. Sami and R. Stefanelli, “Fault-Tolerance and Functional Reconfiguration in VLSI Arrays,” in Proc. Int’l Conf. Circuits and Systems, pp. 643-648, 1986.Google Scholar
  10. [10]
    H.Y. Youn and A.D. Singh, “An Efficient Channel Routing Algorithm for Defective Arrays,” to appear in Proc. IEEE Int’l Conf. on Computer-Aided Design, Nov. 1989.Google Scholar
  11. [11]
    H.Y. Youn and A.D. Singh, “A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI,” in Proc. Int’l Conf. Parallel Processing, pp. 1261-265, Aug. 1989.Google Scholar
  12. [12]
    F.P. Preparata and J. Vuillemin, “The Cube-Connected Cycles: A versatile network for parallel computation,” Commun. ACM, vol. 24, pp. 300–309, May 1981.MathSciNetCrossRefGoogle Scholar
  13. [13]
    J.J. Shen and I. Koren, “Yield Enhancement Designs for WSI Cube-Connected Cycles,” in Proc. Int’l Conf. Wafer Scale Integration, pp. 289-298, Jan. 1989.Google Scholar
  14. [14]
    M.S. Krishnan and J.P. Hayes, “An Array Layout Methodology for VLSI Circuits,” IEEE Trans. Comput. vol. c-35, pp. 1055–1067, Dec. 1986.CrossRefGoogle Scholar
  15. [15]
    P. Banerjee, “The Cubical Connected Cycles: A Fault-Tolerant Parallel Computation Network,” IEEE Trans. Comput. vol. c-37, pp. 632–636, May 1988.CrossRefGoogle Scholar
  16. [17]
    J.I. Raffel et al., “A Wafer-Scale Digital Integrator Using Restnicturable VLSI,” IEEE J. of Solid-State Circuits, vol. sc-20, pp. 399–406, Feb. 1985.CrossRefGoogle Scholar
  17. [18]
    F. Lombardi, R. Negrini, and R. Stefanelli, “Reconfiguration of VLSI arrays: A Covering Approach,” in Proc. 17tli Int’l Symp. Fault-Tolerant Computing, pp. 251-256, June 1987.Google Scholar
  18. [19]
    H.Y. Youn and A.D. Singh, “On Implementing Large Binary Tree Architectures in VLSI and WSI,” IEEE Trans. Comput. vol. c-38, pp. 526–537, April 1989.CrossRefGoogle Scholar
  19. [20]
    A.D. Singh and H.Y. Youn, “Efficient Restructuring Schemes for Wafer Scale Processor Arrays,” in Proc. 1988 Int’l Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 1988.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • H. Y. Youn
    • 1
  • A. D. Singh
    • 1
    • 2
  • J. H. Kim
    • 1
    • 3
  1. 1.Dept. of Computer SciencesUniversity of North TexasDentonUSA
  2. 2.Dept. of Electrical & Computer EngineeringUniversity of MassachusettsAmherstUSA
  3. 3.The CACSUniversity of SW LouisianaLafayetteUSA

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