Yield Model with Critical Geometry Analysis for Yield Projection from Test Sites on a Wafer Basis with Confidence Limits

Abstract

A yield model, based on test site data and layout analysis of yield-sensitive critical geometries, has been developed for a two-level metal, twin-tub 1.25μm CMOS silicon IC process. This yield model can be extended to other CMOS technologies. For each yield-loss mechanism, electrical test results from the test sites and the critical geometries extracted from a particular IC chip layout database are used in the model to predict the components of the IC chip yield and the total chip functional yield with a statistical confidence interval based on the Poisson distribution. An experimental implementation in which test sites and memory chips are fabricated in equal numbers on the same wafer makes it feasible to model the memory chip yield on a wafer-by-wafer basis. The wafer-by-wafer analysis is of interest in cases where there is considerable variation within a wafer lot. Examples are given of lots in which individual wafers are well modeled over a wide range of memory chip yield. In addition, an example is given of a lot in which some wafers are not well modeled in comparison with actual functional yields, indicating that some mechanisms are operative which have not been monitored.