Yield Model with Critical Geometry Analysis for Yield Projection from Test Sites on a Wafer Basis with Confidence Limits

  • C. M. Drum
  • D. L. Gerlach


A yield model, based on test site data and layout analysis of yield-sensitive critical geometries, has been developed for a two-level metal, twin-tub 1.25μm CMOS silicon IC process. This yield model can be extended to other CMOS technologies. For each yield-loss mechanism, electrical test results from the test sites and the critical geometries extracted from a particular IC chip layout database are used in the model to predict the components of the IC chip yield and the total chip functional yield with a statistical confidence interval based on the Poisson distribution. An experimental implementation in which test sites and memory chips are fabricated in equal numbers on the same wafer makes it feasible to model the memory chip yield on a wafer-by-wafer basis. The wafer-by-wafer analysis is of interest in cases where there is considerable variation within a wafer lot. Examples are given of lots in which individual wafers are well modeled over a wide range of memory chip yield. In addition, an example is given of a lot in which some wafers are not well modeled in comparison with actual functional yields, indicating that some mechanisms are operative which have not been monitored.


Defect Density Lateral Short Test Structure Gate Oxide Probe Yield 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    W.J. Bertram, “Yield and Reliability”, in VLSI Technology, ed. S.M. Sze, McGraw-Hill, New York, 1983.Google Scholar
  2. 2.
    A.V. Ferris-Prabhu, “Defects, Faults, and Semiconductor Device Yield”, International Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 6–7, 1988, IEEE Computer Society, p. 1.1-1 to 1.1-12.Google Scholar
  3. 3.
    C.H. Stapper, Jr., “Modeling of Defects in Integrated Circuit Photolithographic Patterns,” IBM J. Res. Dev., vol.28(4), pp.461–475, July 1984.CrossRefGoogle Scholar
  4. 4.
    R. Glang, “Measurement and Distribution of Faults on Defect Test Site Chips”, International Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 6–7, 1988, IEEE Computer Society, p.3.1-1 to 3.1-12.Google Scholar
  5. 5.
    M.A. Mitchell, “Defect Test Structures for Characterization of VLSI Technology”, Solid State Technology, Vol.28, no.5, pp.207–213, (May 1985).Google Scholar
  6. 6.
    W. Lukaszek, W. Yarbrough, T. Walker, J. Meindl, “CMOS Test Chip Design for Process Problem Debugging and Yield Prediction Experiments”, Sol. St. Tech., Vol.29, No.3, pp.87–93, March 1986.Google Scholar
  7. 7.
    C. Alcorn, D. Dworak, N. Haddad, W. Henley, and P. Nixon, “Kerf Test Structure Designs for Process and Device Characterization”, Sol. St. Technology, Vol.28, no.5, p.229, (May 1985).Google Scholar
  8. 8.
    C.H. Stapper, Jr. “On A Composite Model to the IC Yield Problem”, IEEE J. Sol. St. Circuits, vol. SC-10, pp.537–539, Dec. 1975.CrossRefGoogle Scholar
  9. 9.
    S. Magdo, “Yield Model for Projection from Test Site”, International Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 6–7, 1988, IEEE Computer Society, p.3.4-1 to 3.4-9.Google Scholar
  10. 10.
    U. Kaempf, “Statistical Significance of Defect Density Estimates”, 1988 IEEE Proc. Microelect. Test Structures, Vol. 1, p.107, 1988.CrossRefGoogle Scholar
  11. 11.
    It may be shown for random variables X, Y, and Z for which Z = XY that The fourth-order term in the brackets on the right is usually negligible. See Bevington, P.R., “Data Reduction and Error Analysis for the Physical Sciences”, McGraw-Hill, New York, 1969.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • C. M. Drum
    • 1
  • D. L. Gerlach
    • 1
  1. 1.AT&T Bell LaboratoriesAllentownUSA

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