Arithmetic-Based Diagnosis in VLSI Array Processors
Existing literature on reliable VLSI array processors can be divided into two categories: easy-testable techniques and fault-tolerant techniques. The easy-testable techniques allow an array to be modified in such a way that the testing time is independent of the array size  – . This approach exploits the structural properties of iterative arrays which are modeled as combinational circuits. Different testability conditions have been established ,  to determine the observability and controllability of a test vector. Still, these approaches may be impractical since they assume an exhaustive testing of a single processor in the array. The fault-tolerant techniques which do not require a massive redundancy utilize algorithmic properties of matrix operations , . The methods encode data at a high level, and algorithms are designed to operate on encoded data and produce encoded i. e. corrected output data. However the approach has to be “customized” any time it is applied to a specific algorithm.
KeywordsMultiple Fault Combinational Circuit Subsequent Successor Faulty Processor Reconfiguration Scheme
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- D. Sciuto and F. Lombardi, “New conditions for testability of two-dimensional bilateral arrays”, Proc. Int. Conf. on Systolic Systems, pp. 495-504, May 1988.Google Scholar
- W.S. Song and B.R. Musicus, “A fault-tolerant architecture for a parallel digital signal processing machine”, ICCD’87, Oct. 1987.Google Scholar
- W. Shen and A.Y. Oruc, “Mapping algebraic formulas onto mesh-connected processor arrays,” Proc. 20th Ann. Conf. Info. Sci. & Syst., Princeton, NJ, Mar. 1986.Google Scholar