Abstract
A large number of reconfiguration schemes have been presented for defect tolerant mesh arrays. Here a number of such schemes will be compared. Area and speed based measures are presented, along with a summary of the methods required to estimate area overhead, processor utilization, yield and speed.
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Franzon, P.D. (1990). Comparison of Reconfiguration Schemes for Defect Tolerant Mesh Arrays. In: Stapper, C.H., Jain, V.K., Saucier, G. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-9957-6_13
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DOI: https://doi.org/10.1007/978-1-4757-9957-6_13
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