Scanning Tunneling Microscopy for Very Large-Scale Integration (VLSI) Inspection

Abstract

This paper discusses the efforts toward overcoming the difficulty in the inspection and measurement of submicrometer structures of very large-scale integration (VLSI) circuitry. The microelectronic industry has been using finer line-width and spacing to build denser circuitry. When the lines and spacings are smaller than the light wavelength, the traditional optical microscope is no longer able to image the fine lines due to light diffraction.

A new method of surface profiling and dimensional measurement of submicron VLSI structures using scanning tunneling microscopy (STM) has been successfully tested. An improved technique for etching sharp and slender STM probes has been developed, enabling the STM to be applied to high-density, high-rise microelectronic structures and reducing the measurement error caused by the probe geometry. Probes with an ideal tip geometry, with a tip angle less than 3° and a radius of 0.03 µm within 1 µm from the tip, can be consistently produced and are believed to be state-of-the-art. Furthermore, the methods of side wall profiling and true profile reconstruction are developed to avoid the probe geometrical effect, making it possible for STM to obtain an accurate topographical profile without cleaving the sample and viewing it from the edge as needed by scanning electron microscopy (SEM).

Compared to scanning electron microscopy SEM, STM operates in air, provides three-dimensional imaging and yields better resolution; therefore, STM has a greater potential than SEM. The measurement error caused by the geometry of the probe, the only outstanding issue affecting STM accuracy, is explored in detail. The same techniques developed in this study can also be applied to atomic force microscope (AFM), a derivative of STM, for profiling and measuring nonconductive samples.