Algorithms for High-Performance Computing with Smart Pixels
One of the major problems in current parallel high-performance computing systems are limitations in the I/O-bandwidth. This is not only a problem on board level communication but also for chip-to-chip and even gate-to-gate interconnections especially in parallel computers. Optical interconnections between in VLSI technology manufactured electronic circuits as aspired in so-called smart pixels systems may offer in the future a solution1. This paper presents well-suited algorithms and architectures for future smart pixels systems consisting of monolithically integrated photodiodes and electronic circuits, which are hybrid mounted to vertical surface emitting laser diodes (VCSEL)2.
KeywordsProcessing Element Systolic Array Full Adder Gate Delay Symbolic Substitution
Unable to display preview. Download preview PDF.
- 1.J.A. Neff, “3D-Computers with smart pixels”, IEEE/LEOS Summer Topical Meeting 92 on Integrated Optoelectronics, Santa Barbara, August 1992Google Scholar
- 2.J.W. Parker, “ESPRIT II — A European Collaborative Programme in Optical Interconnects” in: Digest of Int. Optical Computing Conference, Kobe, Japan 1990Google Scholar
- 3.T.C. Chen, “Automatic Computation of Exponentials, Logarithms, Ratios and Square Roots,” IBM Journal Res. and Dev., July 1972, pp. 380–388Google Scholar
- 4.D. Fey, “Computer-aided design of digital opto-electronic systems with HADLOP”, in: S.D. Smith, R.F. Neal (eds.), “Optical Information Technology”, Springer 1993Google Scholar
- 5.D. Fey, K.H. Brenner, “Digital Optical Arithmetic based on Systolic Arrays and Symbolic Substitution Logic”, Int. Journ. of Optical Computing 1, (1990) 153–167Google Scholar