Instruction Fetch Hardware

Abstract

One of the difficult tasks of keeping a high speed processor busy is to make sure that it has a constant supply of instructions and to make sure that they are supplied quickly. This requires a very high bandwidth for both instructions and data. For MIPS-X, when both an instruction and data are required, the peak bandwidth required is 160 Mbytes/s. Building a memory system to support this would not be simple and transferring this amount of data across the pins of a VLSI chip would have been difficult with the packaging technology available at the time. MIPS-X uses an on-chip instruction cache to reduce the memory bandwidth requirements. Putting an instruction cache on-chip also makes it possible to fetch new instructions every cycle if the instructions are in the cache.