Vector Processes

  • Roland N. Ibbett


The need to provide facilities for processing sequences of vector elements was recognised in the very early days of digital computer design. The von Neumann concept, for example, included the notion of allowing instructions to be treated as data, which meant that the address part of an instruction accessing a vector element could be incremented during the execution of a program loop and thus produce the effect of processing a vector. In practice, however, this technique allows so much scope for program error that even the very first stored program computer (the Manchester Mark 1) used B-lines instead, and this latter technique has been used almost universally ever since. Thus virtually any digital computer can be used to process vectors. The differences between machines lie in the addressing facilities which they provide to support accesses to data structures, and whether or not they include instructions which implicitly process a sequence of vector elements. Computers with this latter facility have been described by Flynn [40] as Single Instruction Multiple Data (SIMD) arrangements, in contrast with the Single Instruction Single Data (SISD) arrangement of conventional computers. We have already met two examples of SIMD machines in the TI ASC and the CRAY-1 and in this chapter we shall be considering the CDC STAR-100 and CYBER 205 computers. First, however, we shall consider the SISD vector addressing facilities found in MU5 (and by implication machines at the top of the ICL 2900 Series), and also the SIMD string processing orders in MU5.


Central Memory Register File Single Instruction Multiple Data Clock Period Vector Processing 
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Copyright information

© Roland N. Ibbett 1982

Authors and Affiliations

  • Roland N. Ibbett
    • 1
  1. 1.Computer ScienceUniversity of ManchesterUK

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