In any computer the execution of a single instruction requires various activities to be performed, such as instruction accessing, instruction interpretation, operand accessing and arithmetic. If separate hardware units carry out these activities their operations can be overlapped to give an increased rate of completion of instructions. This technique, first introduced in computers such as Atlas and Stretch, has become known as ‘pipeline concurrency’. In a pipeline computer several partially completed instructions are in progress concurrently, and although the time to complete any one instruction is still limited by the sum of the times for the various activities, the rate at which instructions progress through the pipeline is only limited by the time for an individual activity. In Atlas and Stretch the number of concurrent operations was of the order of four. In more recent designs the pipeline concurrency principle has been extended to several tens of instructions and used in both arithmetic and instruction processing units. In this chapter we shall consider the design of the MU5 Primary Operand Unit as an example of the latter and the Texas Instruments Advanced Scientific Computer (TI ASC) as an example of the former. In addition we shall consider some techniques used in the IBM System/360 Model 195 to overcome problems which arise in pipeline designs.
KeywordsControl Transfer Reservation Station High Performance Computer Arithmetic Unit Execution Unit
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