Abstract
This chapter presents the many enhancements to Verflog that SystemVerilog adds for representing and working with design hierarchy. The topics that are discussed include:
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Module prototypes
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Nested modules
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Simplified netlists of module instances
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Netlist aliasing
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Passing values through module ports
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Port connections by reference
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Enhanced port declarations
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Parameterized data types and polymorphism
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Variable declarations in blocks
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© 2004 Springer Science+Business Media Dordrecht
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Sutherland, S., Davidmann, S., Flake, P. (2004). SystemVerilog Design Hierarchy. In: SystemVerilog For Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6682-0_8
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DOI: https://doi.org/10.1007/978-1-4757-6682-0_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6684-4
Online ISBN: 978-1-4757-6682-0
eBook Packages: Springer Book Archive