SystemVerilog Procedural Statements

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

Abstract

SystemVerilog adds several new operators and procedural statements to the Verilog language that allow modeling at a more abstract, C-like level. Additional enhancements convey the designer’s intent, helping to ensure that all software tools interpret the procedural statements in the same way. This chapter covers these operators and procedural statements, and offers guidelines on how to properly use these new constructs.

Keywords

Decrement Operator Decision Sequence Combinational Logic Race Condition Sequential Logic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2004

Authors and Affiliations

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

There are no affiliations available

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