Abstract
SystemVerilog extends Verilog’s built-in data types and enhances how literal values can be specified. This chapter explains these enhancements and offers recommendations on proper usage. A number of small examples illustrate these enhancements in context. Subsequent chapters contain other examples that utilize SystemVerilog’s enhanced data types and literal values. The next chapter covers another important enhancement to data types, user-defined types.
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© 2004 Springer Science+Business Media Dordrecht
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Sutherland, S., Davidmann, S., Flake, P. (2004). SystemVerilog Literal Values and Built-in Data Types. In: SystemVerilog For Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6682-0_2
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DOI: https://doi.org/10.1007/978-1-4757-6682-0_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6684-4
Online ISBN: 978-1-4757-6682-0
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