SystemVerilog Literal Values and Built-in Data Types

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

Abstract

SystemVerilog extends Verilog’s built-in data types and enhances how literal values can be specified. This chapter explains these enhancements and offers recommendations on proper usage. A number of small examples illustrate these enhancements in context. Subsequent chapters contain other examples that utilize SystemVerilog’s enhanced data types and literal values. The next chapter covers another important enhancement to data types, user-defined types.

Keywords

Data Type Source File Procedural Block Automatic Task Program Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2004

Authors and Affiliations

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

There are no affiliations available

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