Advanced ASIC Sign-Off Features of IEEE 1076.4-2000 And Standards updates to Verilog and SDF

Abstract

In the ASIC industry there is much discussion about design complexity, validation cycle time, tools, and overall design methodology. There are concerns that today’s Electronic Design Automation (EDA) tools and standard organizations cannot keep pace with the requirements placed upon them by growing design complexity. This gap is expected to widen even further with each advancement in semiconductor technology that reduces feature size and allows for even larger, faster, and more complex designs. Intellectual Property (IP), large megacells, cores, and a myriad of rapid design methodologies will only continue to put more pressure on these standards and design tools.