Abstract
One of the strengths of Hewlett-Packard’s Technical Solutions Lab has been its ability to efficiently develop workstation graphics subsystems by minimizing serial dependencies in the development process. Central to achieving this was the use of C-language functional models of the subsystem ASICs in a flexible, mixed-level, mixed-language simulation environment. Although the first generation of this simulation environment, known as “NGLE” has been used successfully for a number of years, that experience has also revealed several important opportunities for improvement. In this paper, we describe the next generation of this environment, called the Graphics Product Simulator (GPS), and the improvements it brings. These include support for threaded C-language modeling, an improved method of mixing C-language and Verilog models, dual platform (Windows NT and Unix) support, and improved system-level modeling facilities.
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References
Burgoon, David A., “Achieving Concurrent Engineering for Complex Subsystem Design: The Case for Hardware Functional Modeling using C,” Proceedings of the DesignCon 1998 On-Chip System Design Conference,pp. 357–371.
Burgoon, David A., “A Mixed-Language Simulator for Concurrent Engineering,” Proceedings of the 1998 1VC/VIUF Conference,pp. 114–119.
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© 2002 Springer Science+Business Media New York
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Burgoon, D.A., Powell, E.W., Waitz, J.A.S. (2002). A Mixed C/Verilog Dual-Platform Simulator. In: Mignotte, A., Villar, E., Horobin, L. (eds) System on Chip Design Languages. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6674-5_15
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DOI: https://doi.org/10.1007/978-1-4757-6674-5_15
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5281-3
Online ISBN: 978-1-4757-6674-5
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