Hardware Supported Sorting: Design and Tradeoff Analysis

  • M. Bednara
  • O. Beyer
  • J. Teich
  • R. Wanka
Chapter

Abstract

Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the low performance, while realizing multiprocessor sorting methods on parallel computers is much too expensive with respect to power consumption, physical weight, and cost. We investigate cost/performance tradeoffs for hybrid sorting algorithms that use a mixture of sequential merge sort and systolic insertion sort techniques. We propose a scalable architecture for integer sorting that consists of a uniprocessor and an FPGA-based parallel systolic co-processor. Speedups obtained analytically and experimentally and depending on hardware (cost) constraints are determined as a function of time constants of the uniprocessor and the co-processor.

Keywords

Hybrid Algorithm System Design Automation Speedup Curve FPGA Chip Sorting Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • M. Bednara
    • 1
  • O. Beyer
    • 1
  • J. Teich
    • 1
  • R. Wanka
    • 1
  1. 1.Universität PaderbornPaderbornGermany

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