A Fast and Retargetable Simulator for Application Specific Processor Architectures

  • Frank Engel
  • Johannes Nührenberg
  • Gerhard P. Fettweis


Retargetability allows an easy adoption of a simulator on different processor architectures without a time consuming redesign of all tools. This is evident for an efficient HW/SW codesign.

In this paper we describe a tool set for fast and easy simulation of processor architectures based on a retargetable simulator core. This approach helps to reduce the development time for designing and validating System-on-a-chip (SoC) applications based on a processor core. The use of ANSI C avoids an expensive development of a modeling language.

Our main focus in this paper is on conceptual decisions we made and on the structure of the tool set.


System Design Automation Hardware Description Language Simulation Speed Target Processor Conditional Jump 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedela, A. Neumann, and D. Voggenauer. The MIMOLA Language Version 4.1. Technical report, University of Dortmund, 1994.Google Scholar
  2. [2]
    M. Benz. The Protocol Engine Project. In Workshop on System Design Automation (SDA), 13.-14. Mar. 2000.Google Scholar
  3. [3]
    Cadence Research Center of Computer Science at the Indian Institute of Technology. Hompage. http://www/ Google Scholar
  4. [4]
    DandT Roundtable. Hardware-Software Codesign. IEEE Design é4 Test of Computers,17(1):92–99, jan - mar 2000.Google Scholar
  5. [5]
    G. Fettweis. DSP Cores for Mobile Communications: Where are we going ? In IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), volume I, pages 279–282, 1997.Google Scholar
  6. [6]
    G. P. Fettweis, M. Weiss, W. Drescher, U. Walther, F. Engel, and S. Kobayashi. Breaking New Grounds Over 3000 MOPS: A Broadband Mobile Multimedia Modem DSP. In International Conference on Signal Processing, Applications êand Technology (ICSPAT), pages 1547–1551, 1998.Google Scholar
  7. [7]
    L. H. Goldberg. Vendors Are Counting on Appliance-on-Chip Technology. IEEE Computer, 32 (11): 13–16, Nov. 1999.Google Scholar
  8. [8]
    J. Hennessy. The Future of System Research. IEEE Computer, 32 (8): 27–33, Aug. 1999.CrossRefGoogle Scholar
  9. [9]
    K. Küçükçakar. An ASIP Design Methodology for Embedded Systems. In Workshop on Hardware/Software Codesign (CODES), 1999.Google Scholar
  10. [10]
    R. Leupers, J. Elste, and B. Landwehr. Generation of Interpretive and Compiled Instructions Set Simulators. In Asia and South Pacific Design Automation Conference (ASP-DAC), 1999.Google Scholar
  11. [11]
    S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr. LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. In Design Automation Conference (DA C), 21.-25. June 1999.Google Scholar
  12. [12]
    S. Pees, V. Zivojnovic, A. Ropers, and H. Meyr. Fast Simulation of the TI TMS320C20X DSP. In International Conference on Signal Processing, Applications é4 Technology (ICSPAT), 1997.Google Scholar
  13. [13]
    V. Rajesh. A Generic Aproach to Performance Modeling and Its Application to Simulator Generator. Master’s thesis, Indian Institute of Technologies, 1998.Google Scholar
  14. [14]
    Target Compiler Technologies. The Chess/Checker Retargetable DSP Environment. Hompage. http://www/ Scholar
  15. [15]
    M. Weiß, F. Engel, and G. P. Fettweis. A New Scalable DSP Architecture for System on Chip (soc) Domains. In IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 1999.Google Scholar
  16. [16]
    A. Zeller and D. Lütkehaus. DDD-A Free Graphical Front-End for UNIX Debuggers. Technical report, Braunschweig University of Technology, 1995. Informatik-Bericht No. 95–07.Google Scholar
  17. [17]
    V. Zivojnovic. DSP Processor/Compiler Co-Design: A Quantitative Approach. PhD thesis, Aachen University of Technology, 1998. Shaker Verlag Aachen.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Frank Engel
    • 1
  • Johannes Nührenberg
    • 1
  • Gerhard P. Fettweis
    • 1
  1. 1.Mannesmann Mobilfunk Chair for Mobile Communication SystemsDresden University of TechnologyDresdenGermany

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