Hardware/Software-Architecture and High Level Design Approach for Protocol Processing Acceleration

  • Mirko Benz
  • Georg H. Overbeck
  • Klaus Feske
  • Jens Grusa


Developing hardware support for transport layer protocol processing is a very complex and demanding task. However, for optimal performance hardware acceleration can be required. To cope with this situation we present a high level design approach which targets the development of configurable and reusable components. Therefore we outline the integration of advanced tools for the development of controller systems into our design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of these specialised components is embedded in an approach to develop flexible and configurable protocol engines that can be optimised for specific applications.


Internet Protocol System Design Automation Exception Handling Internet Protocol Address Protocol Processing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Balraj, T.S.; Yemini, Y.: “Putting the Transport Layer on VLSI–the PROMPT Protocol Chip”, in: Pehrson, B.; Gunningberg, P.; Pink, S. (ed.): Protocols for High-Speed Networks, III, North Holland, Stockholm, May 1992, pp. 19–34Google Scholar
  2. [2]
    Benz, M.: “The Protocol Engine Project - An Integrated Hardware/Software Architecture for Protocol Processing Acceleration”, SDA’2000 workshopGoogle Scholar
  3. [3]
    Benz, M.; Engel, F.: “Hardware Supported Protocol Processing for Gigabit Networks”, SDA - Workshop on System Design Automation, 1998Google Scholar
  4. [4]
    Benz, M.; Feske, K.: “A Packet Classification and Validation Unit for Hardware Supported TCP/IP Receive Path Processing”, SDA 2000 workshopGoogle Scholar
  5. [5]
    Engel, E; Nuehrenberg, J.; Fettweis, G.P.: “A Fast and Retargetable Simulator for Application Specific Processor-Architectures”, SDA 2000 workshopGoogle Scholar
  6. [6]
    Feske,K.; Scholz,M.; Doering,G.; Nareike,D.: “Rapid FPGA-Prototyping of a DAB Test Data Generator using Protocol Compiler”, FPL’99, August 30th-Sept 1st 1999, GlasgowGoogle Scholar
  7. [7]
    Feske, K.; Döring, G.; Scholz, M.: “Efficient Design of Structured Data Processing Controllers Using Protocol Compiler and Behavioural Reuse–a Case Study.”, accepted for DATE’2000, Paris, France, 27–30 March 2000Google Scholar
  8. [8]
    Krishnakumar, A.S.: “A Synthesis System for Communication Protocols”, Proceedings of the 5th Annual IEEE International ASIC Conference and Exhibition, Rochester, New York, 1992Google Scholar
  9. [9]
    Krishnakumar, A.S.; Kneuer, J.G.; Shaw, A.J.: “HIPOD: An Architecture for High-Speed Protocol Implementations”, in: Danthine, A.; Spaniol, O. (ed.): High Performance Networking, IV, IFIP, North-Holland, 1993, pp. 383–396Google Scholar
  10. [10]
    Koufopavlou, O.G., Tantawy, A.N., Zitterbart, M.: “Analysis of TCP/IP for High Performance Parallel Implementations”, 17th IEEE Conference on Local Computer Networks, Minneapolis, Minnesota, September 1992Google Scholar
  11. [11]
    Level OneTM IXP1200 Network Processor, Product Brief,, 1999Google Scholar
  12. [12]
    Microsoft Research IPv6 Implementation, 1999Google Scholar
  13. [13]
    Morales, F.A.; Abu-Amara, H.: “Design of a Header Processor for the Psi Implementation of the Logical Link Control Protocol in LANs”, 3rd IEEE International Symposium on High Performance Distributed Computing, San Francisco, 1994, pp. 270–277Google Scholar
  14. [14]
    Pink, Stephen: “TCP/IP on Gigabit Networks, High Performance Networks, Frontiers and Experience”, Kluwer Academic Publishers, 1994, pp 135–156CrossRefGoogle Scholar
  15. [15]
    Schiller, J.H.; Carle, G.J.: “Semi-automated Design of High-Performance Communication Systems”, Proceedings of the 31st Annual IEEE International Conference on System Sciences, HICCS, Hawaii, 1998Google Scholar
  16. [16]
    Seawright, A. et al.: “A System for Compiling and Debugging Structured Data Processing Controllers”, EURO-DAC’96, Geneva, Switzerland, Sept. 16–20, 1996Google Scholar
  17. [17]
    Strayer, W.T.; Dempsey, B.J.; Weaver, A.C.: “XTP - The Xpress Transfer Protocol”, ADDISON-WESLEY, 1992Google Scholar
  18. [18]
    Stevens, W.R.: “TCP/IP Illustrated, Volume 1, The Protocols”, ADDISON-WESLEY, 1994zbMATHGoogle Scholar
  19. [19]
    Stevens, W.R.; Wright, G.R.: “TCP/IP Illustrated, Volume 2, The Implementation”, ADDISON-WESLEY, 1995Google Scholar
  20. [20]
    SYNOPSYS: “V1998. 08 Protocol Compiler User’s Guide”, Synopsys Inc., 1998Google Scholar
  21. [21]
    Virtual Interface Architecture, specification version 1.0,, 1999Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Mirko Benz
    • 1
  • Georg H. Overbeck
    • 1
  • Klaus Feske
    • 2
  • Jens Grusa
    • 2
  1. 1.Department of Computer ScienceDresden University of TechnologyDresdenGermany
  2. 2.FhG IIS Erlangen Department EAS DresdenDresdenGermany

Personalised recommendations