This paper describes a compact, high-speed special purpose processor, which offers a lowcost solution to implement linear time invariant controllers. The controller has been reformulated into a modified state-space representation based on the δ operator, which is optimised for numerical efficiency. This Control System Processor (CSP) has been implemented using a programmable ASIC (ProASIC) device.
KeywordsRegister Bank Program Counter System Design Automation Algorithm Cycle Numerical Requirement
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