Abstract
The potential for switched-current A/D converters in low-voltage, telecommunication applications with a high level of integration is investigated through the test design described in this chapter. A dual, 3 V, 32 MS/s A/D converter was fabricated in a standard digital 5 V, 0.8 mm CMOS process. Fully differential first-generation switched-current circuits with common-mode feedforward are used to implement a 1.5-b/stage pipelined ADC core. Eight time-interleaved ADC cores operating at 4 MS/s are used to achieve a high sample rate. With channel compensation, the measured SFDR is more than 50 dB at 32 MS/s with f in = 1.13 MHz. The ADC-core was measured to have 60.3 dB peak SFDR, 46.5 dB peak SNDR, and approximately 20 MHz input bandwidth. The resolution of the parallel ADC was limited by additional noise and the useful bandwidth was lowered by a fixed-pattern timing error that could not be removed by channel calibration
B. E. Jonsson, and H. Tenhunen, “A Dual 3-V 32-MS/s CMOS Switched-Current ADC for Telecommunication Applications”, Proc. of 1999 Int. Symp. Circuits and Systems, Orlando, Florida, Vol. 2, pp. 343-346, May 1999, IEEE.
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Jonsson, B.E. (2000). A Dual 3-V 32-MS/s CMOS Switched-Current ADC. In: Switched-Current Signal Processing and A/D Conversion Circuits. The Springer International Series in Engineering and Computer Science, vol 561. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6648-6_11
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DOI: https://doi.org/10.1007/978-1-4757-6648-6_11
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