A Design Methodology for High Performance CMOS Current Steering D/A Converters
While in chapter 4 and 5, the emphasis has been put on modelling the static and the dynamic behaviour of the current steering D/A converter architecture, this chapter will cover the design flow for these circuits. In the first section of this chapter, the problem of determining the level of segmentation is addressed. In the remainder of the text, it has been assumed that a segmentation level of 0% matches a fully binary implementation and a segmentation level of 100% represents a fully unary architecture. Both an area based as a mathematically based approach to determine the segmentation degree are discussed. In the following two sections, the choice of the thermometer decoder and the switch driver are addressed. The remaining sections of this chapter describe in detail the dimensioning of all the transistors in the unit current cell (the switch, current source and cascode transistors).
KeywordsCurrent Source Switch Transistor Unary Architecture Segmentation Level Output Voltage Swing
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