Compiler Transformations for DSP Address Calculation
This chapter presents a retargetable approach and prototype tool for the analysis of array references and traversals for efficient address calculation for DSPs. Based on a retargetable architecture model, the approach serves as an enhancement to existing compiler systems or as an aid to architecture exploration. This model is a specification of the addressing resources and operations available on the processor which is used to drive the compiler transformations. In addition to providing the transformation for existing architectures, the model allows the designer to tune the operation of the Address Calculation Unit (ACU) toward the application constraints. Variations on the address registers, index registers and hardwired increment and decrement values may be explored for an algorithm by making simple changes to the specification.
KeywordsDigital Signal Processor Address Generation Induction Variable Array Reference Address Register
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