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Energy-Exposed Instruction Sets

  • Krste Asanović
  • Mark Hampton
  • Ronny Krashinsky
  • Emmett Witchel
Part of the Series in Computer Science book series (SCS)

Abstract

Modern performance-oriented ISAs, such as RISC and VLIW, only expose to software features that impact the critical path through computation. Pipelined microprocessor implementations hide most of the microarchitectural work performed in executing instructions. Therefore, there is no incentive to expose these micro-operations, and their energy consumption is hidden from software.

This work presents energy-exposed hardware-software interfaces to give software more fine-grain control over energy-consuming microarchitectural operations. We introduce software restart markers to make temporary processor state visible to software without complicating hardware exception management. This technique can enable a wide variety of energy optimizations. We implement exposed bypass latches which allow the compiler to eliminate register file traffic by directly targeting the processor bypass latches. Another technique, tag-unchecked loads and stores, allows software to access cache data without a hardware tag check when the compiler can guarantee an access will be to the same line as an earlier access.

Keywords

Register File Cache Line Register Allocation Direct Address Virtual Address 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Furber, S. B. et al. ARM3–32b RISC processor with 4kbyte on-chip cache. In G. Musgrave and U. Lauther, editors, Proceedings IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration (VLSI’89),pages 35–44. Elsevier (North Holland), 1989. ISBN 0 444 88344 4.Google Scholar
  2. [2]
    Intel Corp. Intel Xscale core developers manual,order no. 273473–001 edition, December 2000.Google Scholar
  3. [3]
    G. Kane. MIPS RISC Architecture (R2000/R3000). Prentice Hall, 1989.Google Scholar
  4. [4]
    R. Krashinsky. Microprocessor energy characterization and optimization through fast, accurate, and flexible simulation. Master’s thesis, Massachusetts Institute of Technology, May 2001.Google Scholar
  5. [5]
    Lam, M. S. et al. The SUIF compiler system, 1992–2001. http://www-suif.stanford.edu.
  6. [6]
    Montanaro, J. et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal Solid-State Circuits, 31 (11): 1703–1714, November 1996.CrossRefGoogle Scholar
  7. [7]
    M. Muller. Power efficiency and low cost: The ARM6 family. In Hot Chips IV, August 1992.Google Scholar
  8. [8]
    V. Oklobdzija. Architectural tradeoffs for low power. In Power Driven Microarchitecture Workshop at ISCA98, Barcelona, Spain, June 1998.Google Scholar
  9. [9]
    J. E. Smith and A. R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proc. 12th ISCA, 1985.Google Scholar
  10. [10]
    J. Tseng and K. Asanovic. Energy-efficient register access. In Proceedings of the 13th Symposium on Integrated Circuits and System Design, pages 377–382, Manaus, Amazonas, Brazil, September 2000.Google Scholar
  11. [11]
    W. Walker and H. G. Cragon. Interrupt processing in concurrent processors. IEEE Computer, 28 (6): 36–46, June 1995.CrossRefGoogle Scholar
  12. [12]
    Witchel, E. et al. Direct addressed caches for reduced power consumption. In MICRO 34, Dec 2001.Google Scholar
  13. [13]
    M. Zhang and K. Asanovic. Highly-associative caches for low-power processors. In Kool Chips Workshop, MICRO 33, December 2000.Google Scholar

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Krste Asanović
    • 1
  • Mark Hampton
    • 1
  • Ronny Krashinsky
    • 1
  • Emmett Witchel
    • 1
  1. 1.MIT Laboratory for Computer ScienceCambridgeUSA

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