Energy-Exposed Instruction Sets

  • Krste Asanović
  • Mark Hampton
  • Ronny Krashinsky
  • Emmett Witchel
Part of the Series in Computer Science book series (SCS)


Modern performance-oriented ISAs, such as RISC and VLIW, only expose to software features that impact the critical path through computation. Pipelined microprocessor implementations hide most of the microarchitectural work performed in executing instructions. Therefore, there is no incentive to expose these micro-operations, and their energy consumption is hidden from software.

This work presents energy-exposed hardware-software interfaces to give software more fine-grain control over energy-consuming microarchitectural operations. We introduce software restart markers to make temporary processor state visible to software without complicating hardware exception management. This technique can enable a wide variety of energy optimizations. We implement exposed bypass latches which allow the compiler to eliminate register file traffic by directly targeting the processor bypass latches. Another technique, tag-unchecked loads and stores, allows software to access cache data without a hardware tag check when the compiler can guarantee an access will be to the same line as an earlier access.


Register File Cache Line Register Allocation Direct Address Virtual Address 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Krste Asanović
    • 1
  • Mark Hampton
    • 1
  • Ronny Krashinsky
    • 1
  • Emmett Witchel
    • 1
  1. 1.MIT Laboratory for Computer ScienceCambridgeUSA

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