Abstract
The logic circuits distributing read and write pulses over the rows of an intermediate core are described. The incoming five-digit binary code is written into the first unfilled row, whereas writing is effected from the first filled row.
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References
R. E. Bell, Canad. I. Phys., 34: 563 (1956).
I. V. Shtranikh, Reports of the 5th Scientific-Technological Conference on Nuclear Electronics, Vol. 2, Part 1, p. 47 [in Russian], Atomizdat (1963).
B. E. Zhuravlev, T. Shetet, and V. D. Shibaev, Preprint OIYaI 10–3120 [in Russian], Dubna (1967).
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Goryachev, A.M., Zapevalov, V.A. (1974). Intermediate Memory Device. In: Skobel’tsyn, D.V. (eds) Photomesic and Photonuclear Reactions and Investigation Methods with Synchrotrons. The Lebedev Physics Institute Series, vol 54. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6175-7_12
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DOI: https://doi.org/10.1007/978-1-4757-6175-7_12
Publisher Name: Springer, Boston, MA
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