Intermediate Memory Device

  • A. M. Goryachev
  • V. A. Zapevalov
Part of the The Lebedev Physics Institute Series book series (LPIS, volume 54)


The logic circuits distributing read and write pulses over the rows of an intermediate core are described. The incoming five-digit binary code is written into the first unfilled row, whereas writing is effected from the first filled row.


Logic Circuit Logic Expression Logic Block Photonuclear Reaction Recording Equipment 
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  1. 1.
    R. E. Bell, Canad. I. Phys., 34: 563 (1956).ADSCrossRefGoogle Scholar
  2. 2.
    I. V. Shtranikh, Reports of the 5th Scientific-Technological Conference on Nuclear Electronics, Vol. 2, Part 1, p. 47 [in Russian], Atomizdat (1963).Google Scholar
  3. 3.
    B. E. Zhuravlev, T. Shetet, and V. D. Shibaev, Preprint OIYaI 10–3120 [in Russian], Dubna (1967).Google Scholar

Copyright information

© Springer Science+Business Media New York 1974

Authors and Affiliations

  • A. M. Goryachev
  • V. A. Zapevalov

There are no affiliations available

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