Skip to main content
SpringerLink
Log in

On-line Testing for VLSI—A Compendium of Approaches

  • Chapter
On-Line Testing for VLSI

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 11))

Abstract

This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test, ...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. Nicolaidis, “New TAC—On-Line Testing,” IEEE Test Technology Newsletter, Aug. 1994.

    Google Scholar 

  2. W.C. Carter and P.R. Schneider, “Design of Dynamically Checked Computers,” Proc. 4th Congress IFIP, Edinburgh, Scotland, Aug. 5–10, 1968, Vol. 2, pp. 878–883.

    Google Scholar 

  3. D.A. Anderson, “Design of Self-Checking Digital Networks Using Coding Techniques Coordinates. Sciences Laboratory,” Report R/527, University of Illinois, Urbana, Sept. 1971.

    Google Scholar 

  4. J.E. Smith and G. Metze, “Strongly Fault Secure Logic Networks,” IEEE Trans. on Comp, Vol. C-27, No. 6, June 1978.

    Google Scholar 

  5. E.J. McCluskey and F.W. Clegg, “Fault Equivalence in Combinational Logic Networks,” IEEE Trans. Comp, Vol. C-20, pp. 1286–1293, Nov. 1971.

    Google Scholar 

  6. C.V. Freiman, “Optimal Error Detection Codes for Completely Asymmetric Binary Channels,” Inform. Conte, Vol. 5, pp. 6471, Mar. 1962.

    MathSciNet  Google Scholar 

  7. J.M. Berger, “A Note on Error Detection Codes for Assymmetric Binary Channels,” Inform. Contr, Vol. 4, pp. 68–73, Mar. 1961.

    Article  MATH  Google Scholar 

  8. W.W. Peterson, “On Checking an Adder,” IBM J. Res. Develop, Vol. 2, pp. 166–168, April 1958.

    Article  Google Scholar 

  9. T.R.N. Rao, “Error Coding for Arithmetic Processors,” Academic Press, New York, 1974.

    Google Scholar 

  10. R.W. Hamming, “Error Detecting and Correcting Codes,” BSTJ, Vol. 29, pp. 147–160, 1953.

    MathSciNet  Google Scholar 

  11. M.Y. Hsiao, “A Class of Optimal Minimum Odd-WeightColumn SEC/DED Codes,” IBM JR and D, Vol. 14, pp. 395–403, 1970.

    Article  Google Scholar 

  12. I.S. Reed and G. Solomon, “Polynomial Codes over Certain Finite Fields,” J. Society Ind. Appl. Math, Vol. 8, pp. 300–304, June 1960.

    Article  MathSciNet  MATH  Google Scholar 

  13. R.C. Bose and D.K. Ray-Chaudhuri, “On a Class of Error Correcting Binary Group Codes,” Information and Control, Vol. 3, pp. 68–79, 1960.

    Article  MathSciNet  MATH  Google Scholar 

  14. A. Hocquenghem, “Codes Corecteurs d’Erreurs,” Chiffres 2, pp. 147–156, 1959.

    MathSciNet  MATH  Google Scholar 

  15. J.E. Smith and G. Metze, “The Design of Totally Self-Checking Combinatorials Circuits,” Proc. 7th Fault Tolerant Computing Symposium, Loss Angeless, USA, June 1997.

    Google Scholar 

  16. M. Nicolaidis, “Conception de Circuits Intégrés Autotestables Pour Des Hypothèses de Pannes Analytiques,” Thèse de Docteur Ingenieur en Informatique, Institut National Polytechnique de Grenoble, 1984.

    Google Scholar 

  17. M. Nicolaidis and B. Courtois, “Self-Checking Logic Arrays,” Microprocessors and Microsystems, Butterworth Scientific Ltd., Guildford, UK, May 1989.

    Google Scholar 

  18. K. De, C. Natarajan, D. Nair, and P. Banerjee, “RSYN: A Sys-tern for Automated Synthesis of Reliable Multilevel Circuits,” IEEE Transactions on VLSI Systems, Vol. 2, No. 2, pp. 186– 195, June 1994.

    Google Scholar 

  19. N.A. Touba and E.J. McCluskey, “Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection,” Proc. of Int. Conf. on Comp. Aided Design, 1994.

    Google Scholar 

  20. G. Mago, “Monotone Functions in Sequential Circuits,” IEEE Trans. on Comp, Vol. C-22, No. 10, Oct. 1973.

    Google Scholar 

  21. M. Diaz, “Design of Totally Self-Checking and Fail-safe Sequential Machines,” Proc. 4th Int. Fault Tolerant Computing Symposium, Urbana, IL, 1974.

    Google Scholar 

  22. M. Diaz, J.C. Geffroy, and M. Courvoisier, “On-Set Realization of Fail-Safe Sequential Machines,” IEEE Trans. on Comp, Vol. C-23, pp. 133–138, Feb. 1974.

    Google Scholar 

  23. T. Nanya and T. Kawamura, “A Note on Strongly Fault Secure Sequential Circuits,” IEEE Trans. on Comp, Vol. C-36, pp. 1121–1123, Sept. 1987.

    Google Scholar 

  24. N.K. Jha and S.-J. Wang, “Design and Synthesis of Self-Checking VLSI Circuits,” IEEE Trans. Comp. Aided Des, Vol. 12, pp. 878–887, June 1993.

    Article  Google Scholar 

  25. G.P. Mak, J.A. Abraham, and E.S. Davindson, “The Design of PLAs with Concurrent Error Detection,” FTCS-12, Santa-Monica, June 1982.

    Google Scholar 

  26. W.K. Fuchs, C.H. Chien, and J. Abraham, “Concurrent Error Detection in Highly Structured Logic Arrays,” IEEE J. Solid State Circuits, Vol. SC-22, pp. 583–594, Aug. 1987.

    Google Scholar 

  27. J.-C. Lo, S. Thanawastien, T.R.N. Rao, and M. Nicolaidis, “An SFS Berger Check Prediction ALU and Its Application to Self-Checking Processors Designs,” IEEE Transactions on Computer-Aided Design, Vol. 2, No. 4, April 1992.

    Google Scholar 

  28. U. Sparmann, “On the Check Base Selection Problem for Fast Adders,” Proc. 11th VLSI Test Symposium, Atlantic City, NJ, April 1993.

    Google Scholar 

  29. U. Sparmann and S.M. Reddy, “On the Effectiveness of Residue Code Checking for Parallel Two’s Complement Multipliers,” Proc. 24th Fault Tolerant Computing Symposium, Austin Texas, June 1994.

    Google Scholar 

  30. H.L. Garner, “Generalized Parity Checking,” IRE Trans. on Elect. Comp, Vol. EC-7, pp. 207–213, Sept. 1958.

    Google Scholar 

  31. E. Garcia-Moreno, B. Iniguez, M. Roca, J. Segura, and S. Sureda, “On Chip Dosimeter Compatible Digital CMOS,” 1995 IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  32. F.F. Sellers, M.-Y. Hsiao, and L.W. Bearnson, “Error Detecting Logic for Digital Computers,” McGraw-Hill, New-York, 1968.

    Google Scholar 

  33. O.N. Garcia and T.R.N. Rao, “On the Method of Checking Logical Operations,” Proc. 2nd Annual Princeton Conf Inform. Sci. Sys, 1968, pp. 89–95.

    Google Scholar 

  34. T.G. Gaddes, “An Error Detecting Binary Adder: A hardware Shared Implementation,” IEEE Trans. Comp, Vol. C-19, pp. 34–38, Jan. 1970.

    Google Scholar 

  35. M. Nicolaidis, “Efficient Implementation of Self-Checking Adders and ALUs,” Proc. 23rd Fault Tolerant Computing Symposium, Toulouse France, June 1993.

    Google Scholar 

  36. R.O. Duarte, M. Nicolaidis, H. Bederr, and Y. Zorian, “Efficient Fault-Secure Shifter Design,” Journal of Electronic Testing, Theory and Applications (JETTA), Vol. 12, pp. 7–20, 1998.

    Article  Google Scholar 

  37. M. Nicolaidis, R.O. Duarte, S. Manich, and J. Figueras, “Achieving Fault Secureness in Parity Prediction Arithmetic Operators,” IEEE Design and Test of Computers, April-June 1997.

    Google Scholar 

  38. W.W. Peterson and E.J. Weldon, `Error-Correcting Codes,“ Second edition, The MIT press, Cambridge, Massachusetts, 1972.

    Google Scholar 

  39. A. Avizienis, G.C. Gilley, F.P. Mathur, D.A. Rennels, J.A. Rohr, and D.K. Rubin, “The STAR (Self-Testing and Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design,” IEEE Transactions on Computers, Vol. C-20, pp. 1312–1321, Nov. 1971.

    Google Scholar 

  40. A. Avizienis, “Arithmetic Algorithms for Error-Coded Operands,” IEEE Trans. on Comput, Vol. C-22, No. 6, pp. 567–572, June 1973.

    Google Scholar 

  41. R.O. Duarte, I.A. Noufal, and M. Nicolaidis. “A CAD Framework for Efficient Self-Checking Data Path Design,” IEEE International On-Line Testing Workshop, Crete, Greece, July 1997.

    Google Scholar 

  42. F. Busabaand P.K. Lala, “Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors,” JETTA, Vol. 5, pp. 19–28, April 1994.

    Google Scholar 

  43. V.V. Saposhnikov, VI.V. Saposhnikov, A. Morosov, and

    Google Scholar 

  44. M. Gossel, “Design of Self-Checking Unidirectional Combinational Circuits with Low Area Overhead,” 2nd IEEE Intl. On-Line Testing Workshop, Saint Jean de Luz, Biarritz, France, July 1996.

    Google Scholar 

  45. VI.V. Saposhnikov, A. Dmitriev, M. Gossel, and V.V. Saposhnikov, “Self-Dual Parity Checking-A New Method for On-Line Testing,” 14th IEEE VLSI Test Symposium, Princeton, N.J., April-May 1996.

    Google Scholar 

  46. E. Bohl, T.H. Lindenkreuz, and R. Stephen, “The Fail-Stop Controller AEI 1,” Proc. 1997Int. Test Conf, Washington D.C., Nov. 1997.

    Google Scholar 

  47. M. Nicolaidis and B. Courtois, “Layout Rules for the Design of Self-Checking Circuits,” VLSI Conf, Tokyo, 1985.

    Google Scholar 

  48. M. Nicolaidis and B. Courtois, “Design of Self-Checking Circuits Using Unidirectional Error Detecting Codes,” Proc. of the 16th FTCS, Vienna, Austria, July 1986.

    Google Scholar 

  49. M. Nicolaidis, “Shorts in Self-Checking Circuits,” Proc. Int. Test Conf, Washington, D.C., Sept. 1987, pp. 408–417.

    Google Scholar 

  50. T. Nanya, “Effects Undetectable Bridging Faults in SelfCheckingg PLAs,” Presented in European Design for Testability Workshop, Segovia, Spain, June 1990.

    Google Scholar 

  51. J.C. Lo, J.C. Daly, and M. Nicolaidis, “Desgn of Static CMOS Self-Checking Circuits Using Built-In Current Sensing,” Proc. Int. Conf on Fault Tolerant Computing (FTCS),Boston MA, June 1992.

    Google Scholar 

  52. M. Nicolaidis and Courtois B., “Strongly Code Disjoint Checkers,” IEEE Transactions on Computers, June 1988.

    Google Scholar 

  53. C. Metra, M. Favalli, and B. Ricco, “Self-Checking Detector for Simultaneous On-Line Test of Clock Signals,” 3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  54. J.F. Wakerly, “Error Detecting Codes, Self-Checking Circuits and Applications,” North-Holland, New York, 1978.

    MATH  Google Scholar 

  55. M.J. Ashjaee and S.M. Reddy, “On-Totally Self-Checking Checkers for Separable Codes,” IEEE Trans. on Comp, Vol. C26, pp. 737–744, Aug. 1977.

    Article  MathSciNet  MATH  Google Scholar 

  56. M.A. Marouf and A.D. Friedman, “Design of Self-Checking Checkers for Berger Codes,” Proc. 8th Intl. Fault Tolerant Computing Symposium, Toulouse, France, June 1978.

    Google Scholar 

  57. S.J. Piestrak, “Design of Fast Self-Testing Checkers for Berger Codes,” IEEE Trans. on Comp, Vol. C-36, pp. 629–634, May 1987.

    Google Scholar 

  58. J.-C. Lo and S. Thanawastien, “The Design of Fast Totally Self-Checking Berger code Checkers Based on Berger Code Partitioning,” Proc. 18th Intl. Symposium on Fault Tolerant Computing, Tokyo, Japan, June 1988.

    Google Scholar 

  59. S.J. Piestrak, “Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes,” IEEE Trans. on Comp, Vol. C-39, pp. 360–374, March 1990.

    Google Scholar 

  60. D.A. Anderson and G. Metz, “Design of Totally Self-Checking Check Circuits for m-out-of-n Codes,” IEEE Trans. on Comput, Vol. C-22, pp. 263–269, March 1973.

    Google Scholar 

  61. S.M. Reddy and J.R. Wilson, “Easily Testable Cellular Realization for the (Exactly p)-out-of-n and (p or More)out-of-n Logic Functions.” IEEE Trans. on Comp, Vol. C-23, pp. 98–100, Jan. 1974.

    Google Scholar 

  62. M.A. Marouf and A.D. Friedman, “Efficient Design of Self-Checking Checkers for Any m-out-of-n Codes,” IEEE Trans. on Comp, Vol. C-27, pp. 482–490, June 1978.

    Google Scholar 

  63. S.J. Piestrak, “Design Method of Totally Self-Checking Checkers for m-out-of-n Codes,” Proc. 13th Intl. Fault Tolerant Computing Symposium, Milan, Italy, June 1983.

    Google Scholar 

  64. A.M. Paschalis, D. Nikolos, and C. Halatsis, “Efficient Modular Design of TSC Checkers for m-out-of-n Codes,” IEEE Trans. on Comp, Vol. C-37, pp. 301–309, March 1988.

    Google Scholar 

  65. D.L. Tao, C.R.P. Hartmann, and P.K. Lala, “A General Technique for Designing Totally Self-Checking Checkers for 1-outof-n Codes with Minimum Gate Delay,” IEEE Trans. on Comp, Vol. C-41, pp. 881–886, July 1992.

    Google Scholar 

  66. D. Nikolos, A.M. Paschalis, and G. Philokyprou, `Efficient Design of TSC Checkers for Low-Cost Arithmetic Codes,“ IEEE Trans. on Comp, Vol. C-37, pp. 807–814, July 1988.

    Google Scholar 

  67. J.P. Khakbas and E.J. Mc Cluskey, “Self Testing Embedded Parity Checkers Exhaustive XOR Gate Testing,” Stanford Univ., CRC Rep. 82–10/CSL TN 207, June 1982.

    Google Scholar 

  68. M. Nicolaidis, “Self-Exercising Checkers for Unified Built-in Self-Test (UBIST),” IEEE Transactions on Computer-Aided Design, March 1989.

    Google Scholar 

  69. J. Altet and A. Rubio, “An Approach to On-Line Differential Thermal Testing,” 2nd IEEE International On-Line Testing Workshop, Biarritz, France, July 1996.

    Google Scholar 

  70. K. Arabi and B. Kaminska, “Built-in Temperature and Current Sensors for On-Line Oscillation-Testing,” 1996 IEEE International On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz, France, July 1996.

    Google Scholar 

  71. T. Calin, M. Nicolaidis, and R. Velazco, “Design of Radiation Hardened Memories,” 2nd IEEE International On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz, France, July 1996.

    Google Scholar 

  72. X. Champac, J. Figueras, and A. Rubio, “On a Highly Observable Static and Dynamic Signature for CMOS Circuit Testing,” 2nd IEEE Int. On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz, France, July 1996.

    Google Scholar 

  73. F. Corno, P. Prinetto, and M. Reorda, “Designing of Self-Checking FSMs within Industrial Design Environments,” 1st IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  74. E. Garcia-Moreno, B. Iniguez, M. Roca, J. Segura, and E. Isem, “Clocked Dosimeter Compatible Digital CMOS,” 2nd IEEE Int. On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz, France, July 1996.

    Google Scholar 

  75. C. Knight, A.D. Singh, and V.P. Nelson, “A Concurrent Timing Error Detection Circuit for CMOS,” 3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  76. Y. Maidon, Y. Deval, E. Verdier, J. Tomas, and J.P. Dom, “On Chip IDDX Sensor for Mixed Signal Circuit Test,” 3rd IEEE Ina. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  77. C. Marta, V. Szekely, M. Rencz, and B. Courtois, “Self-Checking Current Output Temperature Sensor for DtTT,” 3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  78. R. Mozuelos, N. Pelaez, M. Martinez, and S. Bracho, “Built-in Current Sensors in Mixed Circuit Test Based on Dynamic Power Supply Current,” 2nd IEEE Int. On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz, France, July 1996.

    Google Scholar 

  79. I. Mucha and H. Manhaeve, “Low Voltage, Current Mirror Based Supply Current Monitors for Double Threshold Voltage Processes,” 3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  80. M. Nicolaidis, T. Calin, and F. Vargas, “A Global Current Testing Approach,” 1st IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  81. J. Rins and J. Figueras, “Circuit Delay Degradation Due to Sensors for IDDQ Testing,” 3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  82. R. Rodriguez-Montanes and J. Figueras, “Current Untestable Irredundant Bridging Defects in CMOS Static Memory Cells,” 1st IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  83. E. Sicard, J.Y. Foumiols, and C. Garres, “Built-in Crosstalk Safety Margin Testing,” 1st IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  84. M. Sidiropulos, V. Stopjakova, H. Manhaeve, and V. Musil, “On-chip IDDX Monitoring for Balanced Analog Circuits,” 3rd IEEE Int On-Line Testing Workshop, Aghi a Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  85. A. Singh, “IDDQ Monitoring for On-Line Detection of Transient and Delay Faults in Self-Checking CMOS Circuits,” 1st IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  86. V. Szekely, Z. Benedek, Z. Kohari, C. Marta, and M. Rencz, “Novel Method for On-Line Thermal Monitoring of Electronic Systems,” Ist IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  87. V. Szekely, M. Rencz, J.M. Karam, M. Lubaszewski, and B. Courtois, “Thermal Monitoring of Self-Checking Systems,” 2nd IEEE Int. On-Line Testing Workshop, Saint-Jean de-Luz, Biarritz, France, July 1996.

    Google Scholar 

  88. F. Vargas, M. Nicolaidis, and Y. Zorian, “Design of MCMs for Space Radiation Environments Based on Current Monitoring,” 1st IEEE Int. On-Line Testing Workshop, Nice, France, July 1995.

    Google Scholar 

  89. F. Vargas, R. Velazco, A.R. Terroso, M. Nicolaidis, and Y. Zorian, “Performance Improvement of Fault-Tolerant Systems Through Chip-Level Current Monitoring,” 3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 1997.

    Google Scholar 

  90. J.M. Soden and C.F. Hawkins, “Electrical Properties and Detection Methods for CMOS IC Defects,” Proc. 1st European Test Conf, April 1991.

    Google Scholar 

  91. F. Vargas, M. Nicolaidis, and B. Hamdi, “Computation of IDDQ Current Based on Quality Requirements,” 11th IEEE VLSI Test Symposium, Atlantic City, USA, April 1993.

    Google Scholar 

  92. K. Baker, “QTAG: A Standard for Test Fixture Based IDDQ//ssQ Monitors,” Proc. 1994 Int Test Conf,Washington, D.C., Oct. 1994.

    Google Scholar 

  93. M. Keating and D. Meyer, “A New Approach to Dynamic IDD Testing,” Proc. 1987 Int. Test Conf,Washington D.C., Sept. 1987.

    Google Scholar 

  94. R. Nigh and W. Maly, “A Self-Testing ALU Using Built-in Current Sensing,” Proc. Custom Integrated Circuit Conference, 1989.

    Google Scholar 

  95. T. Shen, J.C. Daly, and J.-C. Lo, “On-Chip Current Sensing Circuit for CMOS VLSI,” Proc. 10th IEEE VLSI Test Symposium, Atlantic City, N.J., April 1993.

    Google Scholar 

  96. K. Arabi and B. Kaminska, “Design and Realizationof an Accurate Built-In Current Sensor for On-Line Power Dissipation Measurement and IDDQ Testing,” International Test Conference,Washington DC, Nov. 1997.

    Google Scholar 

  97. G. Seydel, E. Bohl, W. Glauert, and A. Soukup, “Test Concept of the Fail-Stop Controller AE 11 using BIST and IDDQ,” 3rd IEEE Int. On-Line Testing Workshop, Crete, Greece, July 1997.

    Google Scholar 

  98. M. Patyra and W. Maly, “Circuit Design for BIC Testing,” Proc. CICC’91, San Diego, CA, May 1991.

    Google Scholar 

  99. A.D. Singh and J.P. Hurst, “Incorporating IDDQ Testing in BIST: Improved Coverage through Test Diversity,” Proc. 12th IEEE VLSI Test Symposium, Cherry Hill, N.J., April 1994.

    Google Scholar 

  100. A. Rubio, J. Figueras, and J. Segura, “Quiescent Current Sensor Circuits in Digital VLSI CMOS Testing,” Electronic Letters, pp. 1204–1206, July 1990.

    Google Scholar 

  101. K. Rius and J. Figueras, “Proportional BIC Sensor for Current Testing,” Journal of Electronic Testing: Theory and Applications, pp. 387–396, Dec. 1992.

    Google Scholar 

  102. Y. Miura and K. Kinoshita, “Circuit Design for Built-in Current Testing,” Proc. of ITC92, Sept. 1992, pp. 873–881.

    Google Scholar 

  103. T.-L. Shen, J.C. Daly, and J.-C. Lo, “A 2-ns Detecting Time, 2-um CMOS Built-in Current Sensing Circuit,” IEEE Journal of Solid State Circuits, pp. 72–77, 1993.

    Google Scholar 

  104. A. Rubio, E. Janssens, H. Casier, J. Figueras, D. Mateo, R. De Pauw, and J. Segura, “A Built-in Quiescent Current Monitor for CMOS VLSI Circuits,” Proc. of EDandTC95, Mar. 1995, pp. 581–585.

    Google Scholar 

  105. J. Rius and J. Figueras, “Detecting IDDQ Defective CMOS Circuits by Depowering,” Proc. of 13th VLSI Test Symposium, pp. 324–329, April 1995.

    Google Scholar 

  106. V. Stopjakovâ, H. Manhaeve, and B. Weber, “Design of a BIC Monitor for IDDQ testing of CMOS VLSI Circuits,” Proc. of ETW96, June 1996, pp. 76–80.

    Google Scholar 

  107. M. Nicolaidis, F. Vargas, and B. Courtois, “Design of Built-In Current Sensors for Concurrent Checking in Radiation Environments,” IEEE Transactions on Nuclear Science,Dec. 1993

    Google Scholar 

  108. S.E. Kerns and B.D. Shafer (Ed.), “The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches,” Proc. IEEE, Nov. 1988, pp. 1470–1509.

    Google Scholar 

  109. F. Vargas and M. Nicolaidis, “SEU Tolerant SRAM Design Based on Current Monitoring,” Proc. 24th IEEE Int. Symposium on Fault Tolerant Computing, Austin, Texas, June 1994.

    Google Scholar 

  110. T. Calin, F. Vargas, M. Nicolaidis, and R. Velazco, “A Low-Cost, Highly Reliable Upset Tolerant SRAM Prototype and Test Results,” IEEE Transactions on Nuclear Science, Dec. 1995.

    Google Scholar 

  111. V. Szekely, Cs. Marta, M. Rencz, Zs. Benedek, and B. Courtois, “Design for Thermal Testability (DfTT) and a CMOS Realization,” In Journal: “Sensors and Actuators,” A-Physical, Vol. A55, No. 1, Special Issue on Thermal Investigations of /Cs and Microstructures (Therminic Workshop 95), July 1996.

    Google Scholar 

  112. V. Szekely, Cs. Marta, Zs. Kohari, and M. Rencz, “CMOS Sensors for On-line Thermal Monitoring of VLSI Circuits,” In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 3, Sept. 1997.

    Google Scholar 

  113. J.-J. Tang, K-J. Lee, and B-D. Liu, “Built-In Intermediate Voltage Testing for CMOS Circuits,” Proc. European Design and Test Conf,Paris, March 1995.

    Google Scholar 

  114. P. Franco and E.J. McCluskey, “On-Line Delay Testing of Digital Circuits,” 12th IEEE VLSI Test Symposium, Cherry Hill, N.J., April 1994.

    Google Scholar 

  115. H. Mine and Y. Koga, “Basic Properties and a Construction Method for Fail-Safe Logical Systems,” IEEE Trans. Elec. Comp, Vol. EC-16, pp. 282–289, June 1967.

    Google Scholar 

  116. K. Futsuhara, N. Sugimoto, and M. Mukaidono, “Fail-Safe Logic Elements Having Upper and Lower Thresholds and Their Application to Safety Control:’ The 18th Intern. Symposium on Fault-Tolerant Computing,Tokyo, June 1988. Digest of Papers of FTCS-I 8, Poster Session, pp. 15–18.

    Google Scholar 

  117. M. Nicolaidis, “Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation,” To appear in IEEE Transactions on Computers Special Issue on Dependability of Computing Systems, Jan. 1998.

    Google Scholar 

  118. L. Rockett, “An SEU Hardened CMOS Data Latch Design,” IEEE Trans. on Nuclear Sc, Vol. NS-35, No. 6, pp. 16821687, Dec. 1988.

    Google Scholar 

  119. S. Whitaker, J. Canaris, and K. Liu, “SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder,” IEEE Trans. on Nuclear Sc, Vol. NS-38, No. 6, pp. 1471–1477, Dec. 1991.

    Google Scholar 

  120. D. Bessot and R. Velazco, “Design of SEU-Hardened CMOS Memory Cells: The HIT Cell,” Proc. 1994 RADECS Conf,pp. 563–570.

    Google Scholar 

  121. M. Nicolaidis and T. Calin, “A Theory of Perturbation Tolerant Asynchronous FSMs and its Application on the Design of Perturbation Tolerant Memories,” 1997 European Test Workshop, Cagliarri, 28–30 May, 1997.

    Google Scholar 

  122. R. Sharma and K.K. Saluja, “An Implementation and Analysis of a Concurrent Built-In Self-Test Technique,” Proc.l8th Intl. Symposium on Fault Tolerant Computing,Tokyo, Japan, June 1998.

    Google Scholar 

  123. M. Nicolaidis, “Theory of Transparent BIST for RAMs,” IEEE Trans. on Computers, Vol. 45, No. 10, Oct. 1996.

    Google Scholar 

  124. C. Metra, M. Favalli, and B. Ricco, “Highly Testable Compact Single Output Comparator,” 15th IEEE VLSI Test Symposium, Monterey, CA, April—May 1997.

    Google Scholar 

  125. S.J. Piestrak, “The Minimal Test Set for Sorting Networks and the Use of Sorting Networks in Self-Testing Checkers for Unordered Codes,Proc. Intl. Symposium on Fault Tolerant Computing, Newcastle upon Tyne, UK, June 1990.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Reliable Integrated Systems Group, TIMA, 46 Avenue Felix Viallet, 38031, Grenoble, France

    M. Nicolaidis

  2. LogicVision, 101-Metro Drive, San Jose, CA, 95110, USA

    Y. Zorian

Authors
  1. M. Nicolaidis
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Y. Zorian
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. TIMA Laboratories, USA

    Michael Nicolaidis

  2. Logic Vision, Inc., USA

    Yervan Zorian

  3. Texas A & M University, USA

    Dhiraj K. Pradan

Rights and permissions

Reprints and permissions

Copyright information

© 1998 Springer Science+Business Media New York

About this chapter

Cite this chapter

Nicolaidis, M., Zorian, Y. (1998). On-line Testing for VLSI—A Compendium of Approaches. In: Nicolaidis, M., Zorian, Y., Pradan, D.K. (eds) On-Line Testing for VLSI. Frontiers in Electronic Testing, vol 11. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6069-9_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4757-6069-9_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5033-8

  • Online ISBN: 978-1-4757-6069-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation