Noise Analysis of Phase-Locked Loops

  • Amit Mehrotra
  • Alberto Sangiovanni-Vincentelli


Phase and delay locked loops (PLL and DLL) are extensively used in microprocessors and digital signal processors for clock generation and as frequency synthesizers in RF communication systems for clock extraction and generation of a low phase noise local oscillator signal from an on-chip voltage controlled oscillator (VCO) which might have a higher open-loop noise performance. The basic block diagram of a PLL is shown in Figure 7.1.


Power Spectral Density Phase Noise Output Spectrum Charge Pump Voltage Control Oscillator 
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  1. 1.
    Or a multiple thereof if frequency dividers are used.Google Scholar
  2. 2.
    The formulation in (7.4) may not be valid when the loop filter is not present. This case is discussed separately in Section 3.Google Scholar
  3. 3.
    I.e., the trajectory of β(t) in (7.5) converges to the solution of (7.6) with probability 1.Google Scholar
  4. 4.
    There is also an exp(—At 1) term in this expression which vanishes asymptotic if A has eigenvalues with positive real parts.Google Scholar
  5. 5.
    This scaling also helps the numerical stability of this computation.Google Scholar
  6. 6.
    Transient analysis may be required anyway for predicting the transient behaviour of the PLL.Google Scholar
  7. 7.
    Oscillator phase noise in dBc/Hz at large ω offset is given by \( 10{\log _{10}}{C_{vco}}{(\frac{{{\omega _0}}}{{{\omega _{offest}}}})^2} \) [112, 115, 116].Google Scholar

Copyright information

© Springer Science+Business Media New York 2004

Authors and Affiliations

  • Amit Mehrotra
    • 1
  • Alberto Sangiovanni-Vincentelli
    • 2
  1. 1.University of Illinois at Urbana-ChampaignUSA
  2. 2.University of CaliforniaUSA

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