Mixed-Mode Simulation and Implementation

  • Resve Saleh
  • Shyh-Jye Jou
  • A. Richard Newton
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 279)

Abstract

This chapter describes the methods involved in implementing a mixed-mode simulator and a tool that is to be used in conjunction with it. The iSPLICE3 program [SAL89A] is used as an implementation case study since it uses many of the algorithms described in the previous four chapters. The chapter begins with an overview of the architecture of iSPLICE3. Then, the mechanisms associated with the implementation of an event scheduler are presented. Following this, event scheduling policies during the transient analysis are described. Next, the techniques used to obtain the dc solution are provided. This is followed by a description of an automatic mixed-mode partitioning tool called iSPLIT [THA92]. This program converts a transistor level description into a mixed-mode description that can be used to drive the iSPLICE3 program. Finally, a large benchmark circuit is used to demonstrate the typical performance of mixed-mode simulators at the end of the chapter.

Keywords

NMOS Transistor PMOS Transistor Logic Node Time Queue Sense Amplifier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • Resve Saleh
    • 1
  • Shyh-Jye Jou
    • 1
  • A. Richard Newton
    • 2
  1. 1.University of IllinoisUSA
  2. 2.University of CaliforniaUSA

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