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High Voltage Devices and Circuits in Standard CMOS Technologies pp 5–49Cite as

Supply Voltage Limits in Standard CMOS Technologies

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Abstract

Various undesirable effects can take place in a low-voltage transistor if one of its terminals is pushed beyond the voltage limit set by the technology. The scope of this chapter is the investigation and modelling of these effects. A particular interest is first focused on the degradation of the device characteristics resulting from channel hot-carrier effects. Then, destructive mechanisms such as, avalanche breakdown. surface breakdown, snapback breakdown, punchthrough breakdown and gate oxide breakdown are analysed. These theoretical considerations are the basics required to implement the design of reliable high-voltage devices.

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Authors and Affiliations

  1. Swiss Federal Institute of Technology, Lausanne, Switzerland

    Hussein Ballan & Michel Declercq

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  1. Hussein Ballan
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  2. Michel Declercq
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© 1999 Springer Science+Business Media Dordrecht

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Ballan, H., Declercq, M. (1999). Supply Voltage Limits in Standard CMOS Technologies. In: High Voltage Devices and Circuits in Standard CMOS Technologies. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-5404-9_2

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  • DOI: https://doi.org/10.1007/978-1-4757-5404-9_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5052-9

  • Online ISBN: 978-1-4757-5404-9

  • eBook Packages: Springer Book Archive

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