Supply Voltage Limits in Standard CMOS Technologies

  • Hussein Ballan
  • Michel Declercq


Various undesirable effects can take place in a low-voltage transistor if one of its terminals is pushed beyond the voltage limit set by the technology. The scope of this chapter is the investigation and modelling of these effects. A particular interest is first focused on the degradation of the device characteristics resulting from channel hot-carrier effects. Then, destructive mechanisms such as, avalanche breakdown. surface breakdown, snapback breakdown, punchthrough breakdown and gate oxide breakdown are analysed. These theoretical considerations are the basics required to implement the design of reliable high-voltage devices.


Breakdown Voltage Depletion Layer Electric Field Distribution nMOS Transistor Gate Current 
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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Hussein Ballan
    • 1
  • Michel Declercq
    • 1
  1. 1.Swiss Federal Institute of TechnologyLausanneSwitzerland

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