Advertisement

Sparse Cluster Design

  • Guy Lemieux
  • David Lewis
Chapter

Abstract

In PLDs, the connections from the CLB inputs and LUT outputs to the LUT inputs are often formed with a full crossbar. Such a high degree of connectivity makes routing easier, but it has significant area overhead. This chapter explores the use of sparse crossbars as an alternative switch matrix inside the clusters. This organisation is called a sparse cluster architecture. The experimental results show that switch densities can be reduced by 50% or more to save 10–18% in area. This switch reduction does not degrade critical-path delay, but some spare cluster inputs are required to compensate for the decrease in routability. Although not explored here, it may be possible to achieve further improvements to area and delay by using CLBs with more LUTs and by calculating delay more accurately.

Keywords

Programmable Logic Channel Width Interconnection Network Benchmark Circuit Tile Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 2004

Authors and Affiliations

  • Guy Lemieux
    • 1
  • David Lewis
    • 2
    • 3
  1. 1.Department of Electrical and Computer EngineeringUniversity of British ColumbiaVancouverCanada
  2. 2.Altera Toronto Technology CentreAltera CorporationCanada
  3. 3.Edward S. Rogers Senior Department of Electrical and Computer EngineeringUniversity of TorontoTorontoCanada

Personalised recommendations