Sparse Cluster Design
In PLDs, the connections from the CLB inputs and LUT outputs to the LUT inputs are often formed with a full crossbar. Such a high degree of connectivity makes routing easier, but it has significant area overhead. This chapter explores the use of sparse crossbars as an alternative switch matrix inside the clusters. This organisation is called a sparse cluster architecture. The experimental results show that switch densities can be reduced by 50% or more to save 10–18% in area. This switch reduction does not degrade critical-path delay, but some spare cluster inputs are required to compensate for the decrease in routability. Although not explored here, it may be possible to achieve further improvements to area and delay by using CLBs with more LUTs and by calculating delay more accurately.
KeywordsProgrammable Logic Channel Width Interconnection Network Benchmark Circuit Tile Size
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