# Multiplication

Chapter

## Abstract

Multiplication is usually regarded as the second most important arithmetic function. However, statistics suggest that in some large scientific programs it occurs as frequently as addition and subtraction combined. As in the previous chapter, this chapter will discuss the procedures involved in multiplication of two binary ‘bit patterns’, and will not discuss the problems of handling signed numbers. Signed multiplication will be described in chapter 4 in the discussion of the representation of negative numbers.

## Keywords

Digital Computer Partial Product Arithmetic Unit Carry Save Adder Serial Adder
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## References

- Booth, A. D., ‘A Signed Binary Multiplication Technique’,
*Q. Jl Mech. appl. Math.*,**4**(1951) 236–40.MathSciNetCrossRefzbMATHGoogle Scholar - This design, like many others on similar lines, is not fast, and is very expensive. de Mori, R., ‘Suggestion for an IC Fast Parallel Multiplier’,
*Electron. Lett*,**5**(1969) 50–1. Yet another design which is not fast, and very expensive.CrossRefGoogle Scholar - Gosling, J. B., ‘Design of Large High Speed Binary Multiplier Units’,
*Proc. I.E.E.*,**118**(1971) 499–505. First description, as such, of the twin-beat multiplier (termed serial—parallel here). Useful assessment of cost effectiveness of multipliers at that time. Relative figures are still relevant.CrossRefGoogle Scholar - Gosling, J. B., Kinniment, D. J., and Edwards, D. B. G., ‘Uncommitted Logic Array Provides Cost Effective Multiplication even for Long Words’,
*Comput. dig. Tech.*,**2**(1979) 113–20.CrossRefGoogle Scholar - Guild, H. H., ‘Fully Iterative Fast Array for Binary Multiplication and Addition’,
*Electron. Lett*,**5**(1969) 263. Another design which is not fast, and very expensive.CrossRefGoogle Scholar - Habibi, A., ‘Fast Multipliers’,
*I.E.E.E. Trans. Comput*,**19**(1970) 153–7.CrossRefzbMATHGoogle Scholar - Kilburn, T., Edwards, D. B. G., and Thomas, G. E., ‘The Manchester Mk II Digital Computing Machine’,
*Proc. I.E.E.*,**107B**Suppl. 2 (1956) 247–68. An early paper describing a carry-save-adder multiplier, though not by that name.Google Scholar - Thornton, J. E.,
*Design of a Computer: CDC 6600*(Scott Foresman, Glenview, Ill, 1970).Google Scholar - Wallace, C. S., ‘A Suggestion for a Fast Multiplier’,
*I.E.E.E. Trans. electronic Comput*,**13**(1964) 14–17. A simultaneous multiplier with carry-save adders.CrossRefzbMATHGoogle Scholar

## Copyright information

© John B. Gosling 1980