Abstract
In concluding this book we summarize the accomplishments. We began with emphasizing the relevance of testing in general and the structural testing in particular. The main contributions of the defect oriented testing are summarized and at the same time its limitations are also highlighted. Furthermore, future trends and research directions are recommended.
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References
S. Chakravarty and P.J. Thadikaran, Introduction to IDDQ Testing, Boston: Kluwer Academic Publishers, 1997.
R. Dekker, F. Beenker and L. Thijssen, “Fault Modeling and Test Algorithm Development for Static Random Access Memories,” Proceedings of International Test Conference, 1988, pp. 343–352.
E.B. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testability,” Journal of Design Automation and Fault Tolerant Computing, vol. 2, no. 2, pp. 165–178, May 1978.
S. Funatsu, N. Wakatsuki and T. Arima, “Test Generation Systems in Japan,” Proceedings of 12th Design Automation Symposium, 1975, pp. 114–122.
R.K. Gulati and C.F. Hawkins, IDDQ Testing of VLSI Circuits, Boston: Kluwer Academic Publishers, 1993.
J. Khare and W. Maly, “Inductive Contamination Analysis (ICA) with SRAM Applications,” Proceedings of International Test Conference, 1995, pp. 552–560.
L. Nederlof, “One Chip TV,” Proceedings of International Solid State Circuits Conference, 1996, pp. 26–29.
M. Sachdev, “A Defect Oriented Testability Methodology for Analog Circuits,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 3, pp. 265–276, June 1995.
J. Schutz, “The Evolution of Microprocessor Design in Response to Silicon Process Evolution,” Proceedings of 21st European Solid State Circuits Conference, 1995, pp. 16–19.
P. Singer, “1995: Looking Down the Road to Quarter-Micron Production,” Semiconductor International, vol. 18, no. 1, pp. 46–52, January 1995.
E. Takeda et al, “VLSI Reliability Challenges: From Device Physics to Wafer Scale Systems,” Proceedings of IEEE, vol. 81, no. 5, pp. 653–674, May 1993.
P. Varma, A.P. Ambler and K. Baker, “An Analysis of the Economics of Self-Test,” Proceedings of International Test Conference, 1984, pp. 20–30.
T.W. Williams and K.P. Parker, “Design for Testability—A Survey,” Proceedings of the IEEE, vol. 71, no. 1, pp. 98–113, January 1983.
T.W. Williams and K.P. Parker, “The National Technology Roadmap for Semiconductors,” San Jose: Semiconductor Industry Assciation, 1995.
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© 1999 Springer Science+Business Media Dordrecht
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Sachdev, M. (1999). Conclusion. In: Defect Oriented Testing for CMOS Analog and Digital Circuits. Frontiers in Electronic Testing, vol 10. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4926-7_8
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DOI: https://doi.org/10.1007/978-1-4757-4926-7_8
Publisher Name: Springer, Boston, MA
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