Abstract
Scan chains are a popular feature in complex ICs. The inherent test complexity of a scan chain is linear with respect to the number of flip-flops it contains. In this chapter, a DFT strategy is outlined such that a scan chain can be tested with very few test vectors by making the chain transparent in the test mode. Such a strategy improves the defect coverage of the IDDQ test for flip-flops. For ICs without scan chains, robust flip-flops are proposed that are inherently IDDQ testable.
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© 1999 Springer Science+Business Media Dordrecht
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Sachdev, M. (1999). Testing Defects in Sequential Circuits. In: Defect Oriented Testing for CMOS Analog and Digital Circuits. Frontiers in Electronic Testing, vol 10. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4926-7_4
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DOI: https://doi.org/10.1007/978-1-4757-4926-7_4
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