Testing Defects in Sequential Circuits

  • Manoj Sachdev
Part of the Frontiers in Electronic Testing book series (FRET, volume 10)

Abstract

Scan chains are a popular feature in complex ICs. The inherent test complexity of a scan chain is linear with respect to the number of flip-flops it contains. In this chapter, a DFT strategy is outlined such that a scan chain can be tested with very few test vectors by making the chain transparent in the test mode. Such a strategy improves the defect coverage of the IDDQ test for flip-flops. For ICs without scan chains, robust flip-flops are proposed that are inherently IDDQ testable.

Keywords

Setup Time Hold Time Propagation Delay Clock Generator Clock Signal 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Manoj Sachdev
    • 1
  1. 1.Philips ResearchThe Netherlands

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