Defects in Logic Circuits and Their Test Implications

  • Manoj Sachdev
Part of the Frontiers in Electronic Testing book series (FRET, volume 10)

Abstract

A substantial amount of research has been carried out since 80s to verify the validity of various fault models. This chapter summarizes some of the earlier work done in this area. During the same time frame, quiescent current measurement technique also known as IDDQ testing became popular owing to its ability to uncover defects in CMOS circuits. Studies were conducted over the relative effectiveness of Boolean (logic) and IDDQ methods of testing for defect detection. Salient features of these studies are reproduced.

Keywords

Logic Gate Complementary Metal Oxide Semiconductor Logic Circuit Gate Oxide Open Defect 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Manoj Sachdev
    • 1
  1. 1.Philips ResearchThe Netherlands

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