# Digital CMOS Fault Modeling and Inductive Fault Analysis

Chapter

## Abstract

We begin with an overview of digital fault models. Different fault models are classified according to the level of abstraction. The merits and shortcomings of these models are reviewed. The second half of the chapter is devoted to the defect oriented fault modeling methodology or Inductive Fault Analysis, as it is popularly known. Unlike the conventional fault modeling methods, IFA takes into account the circuit layout and manufacturing process defects to generate realistic and layout dependent faults.

## Keywords

Fault Modeling Logic Gate Test Vector NAND Gate Delay Fault
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