Abstract
This chapter introduces some key test issues, namely test complexity, quality, reliability and economics, faced by semiconductor test industry. These issues form a basis for subsequent chapters.
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References
M. Abadir and A.P. Ambler, Economics of Electronic Design, Manufacture and Test, Boston: Kluwer Academic Publishers, 1994.
V.D. Agrawal, S.C. Seth and P. Agrawal, “Fault Coverage Requirement in Production Testing of LSI Circuits,” IEEE Journal of Solid State Circuits, vol. SC-17, no. 1, pp. 57–61, February 1982.
A.P. Ambler, M. Abadir and S. Sastry, Economics of Design and Test for Electronic Circuits and Systems, New York: Ellis Horwood, 1992.
K. Baker, “QTAG: A Standard for Test Fixture Based IDDQ/ISSQ Monitors,” Proceedings of International Test Conference, 1994, pp. 194–202.
S.D. Brown, “Field-Programmable Devices: Technology, Applications, Tools,” 2nd Edition, Los Gatos: Stan Baker Associates, 1995.
D.L. Crook, “Evolution of VLSI Reliability Engineering,” Proceedings of International Reliability Physics Symposium, 1990, pp. 2–11.
C. Dislis, J.H. Dick, I.D. Dear and A.P. Ambler, Test Economics and Design For Testability, New York: Ellis Horward, 1995.
F.J. Ferguson and J.P. Shen, “Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis,” Proceedings of International Test Conference, 1988, pp. 475–484.
A.V. Ferris-Prabhu, “Computation of the critical area in semiconductor yield theory,” Proceedings of the European Conference on Electronic Design Automation, 1984, pp. 171–173.
R. Gayle, “The Cost of Quality: Reducing ASIC Defects with IDDQ, At-Speed Testing and Increased Fault Coverage,” Proceedings of International Test Conference, 1993, pp. 285–292.
R. Gulati and C. Hawkins, IDDQ Testing of VLSI Circuits, Boston: Kluwer Academic Publishers, 1993.
C. Hawkins, and J. Soden, “Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs,” Proceedings of International Test Conference, 1986, pp. 443–451.
E. R. Hnatek, “IC Quality–Where Are We?” Proceedings of International Test Conference, 1987, pp. 430–445.
E. R. Hnatek, Integrated Circuits Quality and Reliability, New York: Marcel Dekker, Inc., 1987.
M. Inoue, T. Yamada and A. Fujiwara, “A New Testing Acceleration Chip for Low-Cost Memory Test,” IEEE Design and Test of computers, vol. 10, pp. 15–19, March 1993.
J. Khare and W. Maly, From Contamination to Defects, Faults and Yield Loss, Boston: Kluwer Academic Publishers, 1996.
P. Mazumder and K. Chakraborty, Testing and Testable Design of High-Density Random-Access Memories, Boston: Kluwer Academic Publishers, 1996.
W. Maly and M. Patyra, “Design of ICs Applying Built-in Current Testing,” Journal of Electronic Testing: Theory and applications, vol. 3, pp. 397–406, November 1992.
E.J. McCluskey and F. Buelow, “IC Quality and Test Transparency,” Proceedings of International Test Conference, 1988, pp. 295–301.
S. D. McEuen, “IDDq Benefits,” Proceedings of VLSI Test Symposium, 1991, pp. 285–290.
B. Mustafa Pulat and L. M. Streb, “Position of Component Testing in Total Quality Management (TQM),” Proceedings of International Test Conference, 1992, 362–366.
R. Perry, “IDDQ testing in CMOS digital ASICs,” Journal of Electronic Testing: Theory and applications, vol. 3, pp. 317–325. November 1992.
M. Sachdev, “Reducing the CMOS RAM Test Complexity with IDDQ and Voltage Testing,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 2, pp. 191–202, April 1995.
M. Sachdev, “A Defect Oriented Testability Methodology for Analog Circuits,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 3, pp. 265–276, June 1995.
A. Schafft, D. A. Baglee and P. E. Kennedy, “Building-in Reliability: Making it Work,” Proceedings of the International Reliability Physics Symposium, 1991, pp. I - 7.
Semiconductor International, vol. 14, no. 5, pp. 62, May 1991.
S.C. Seth and V.D. Agrawal, “Characterizing the LSI Yield Equation from Wafer Test Data,” IEEE Transactions on Computer-Aided Design, vol. CAD-3, no. 2, pp. 123–126, April 1984.
P. Singer, “1995: Looking Down the Road to Quarter-Micron Production,” Semiconductor International, vol$118, no. I, pp. 46–52, January 1995.
J.M. Soden, C.F. Hawkins, R.K. Gulati and W. Mao, “IDDQ Testing: A Review,” Journal of Electronic Testing: Theory and applications, vol. 3, pp. 291–303, November 1992.
M. Syrzycki, “Modeling of Spot Defects in MOS Transistors,” Proceedings of International Test Conference, 1987, pp. 148–157.
E. Takeda et al., “VLSI Reliability Challenges: From Device Physics to Wafer Scale Systems,” Proceedings of IEEE, vol. 81, no. 5, pp. 653–674, May 1993.
P. Varma, A.P. Ambler and K. Baker, “An Analysis of The Economics of Self-Test,” Proceedings of International Test Conference, 1984, pp. 20–30.
P. Wiscombe, “A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels,” Proceedings of International Test Conference, 1993, pp. 293–299.
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© 1999 Springer Science+Business Media Dordrecht
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Sachdev, M. (1999). Introduction. In: Defect Oriented Testing for CMOS Analog and Digital Circuits. Frontiers in Electronic Testing, vol 10. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4926-7_1
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DOI: https://doi.org/10.1007/978-1-4757-4926-7_1
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