Demonstrator Designs

  • Francky Catthoor
  • Koen Danckaert
  • Chidamber Kulkarni
  • Erik Brockmeyer
  • Per Gunnar Kjeldsberg
  • Tanja Van Achteren
  • Thierry Omnes
Chapter

Abstract

In this chapter several complete applications will be explored to demonstrate the large impact which can be achieved by the DTSE approach. The main focus lies on target architecture styles where at least partly predefined memory organisations are present. But part of the organisation, especially on-chip, can also be customisable still. The demonstrators have been selected from different target application domains to substantiate our claims that data-dominant applications occur in a broad domain, of significant industrial relevance.

Keywords

Execution Time Motion Estimation Cache Size Storage Management Memory Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Francky Catthoor
    • 1
  • Koen Danckaert
    • 1
  • Chidamber Kulkarni
    • 1
  • Erik Brockmeyer
    • 1
  • Per Gunnar Kjeldsberg
    • 2
  • Tanja Van Achteren
    • 3
  • Thierry Omnes
    • 1
  1. 1.IMECLeuvenBelgium
  2. 2.Norwegian Univ. of Sc. and Tech. (NTNU)TrondheimNorway
  3. 3.Katholieke Universiteit LeuvenLeuvenBelgium

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