Storage Cycle Budget Distribution and Access Ordering

Abstract

In many cases, a fully customized (on-chip) memory architecture can give superior memory bandwidth and power characteristics over traditional hierarchical memory architecture including data caches. This is especially so when the application is very well analyzable at compile-time. In an embedded context this is typically quite well achievable because the application (set) to be mapped is usually fully fixed and the on-chip memory organisation can be at least partly tuned towards this application (set).