Architecture and Design of 1-D Enhanced Cellular Neural Network Processors for Signal Detection

  • Michelle Yibing Wang
  • Bing J. Sheu
  • Theodore W. Berger
  • Wayne C. Young
  • Austin Kwang-Bo Cho


One-dimensional cellular array processor architecture and design for neural-based partial response (PR) signal detection are presented. Analog parallel computing approaches have many attractive advantages in achieving low power, low cost, and faster processing speed by its uniquely coupled parallel and distributed processing nature. In this paper, we describe the maximum likelihood sequence estimation (MLSE) algorithm for PR signals, the enhanced Cellular Neural Network (CNN) processor array architecture to realize the detection algorithm, and system performance evaluation. Analytical models and simulations on a design example of the detector have been employed to demonstrate the advantages of this scalable VLSI architecture. A processing rate of 265 Mbps was achieved for a prototype detector on a silicon area of 5.14 mm by 5.81 mm is a 1.2µm CMOS technology. The processing rate can be beyond 1Gbps if it is implemented in the same amount of silicon area by using 0.5µm CMOS technology. Such promising results clearly demonstrate the ability to meet the needs in future high speed data communication by VLSI realization of maximum likelihood sequence detectors based on the enhanced cellular neural network paradigm.


Cellular Neural Network Very Large Scale Integration Processor Array Silicon Area Connection Matrix 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    P. Kabal and S. Pasupathy, “Partial response signaling.” IEEE Trans. on Communications 23 (9), pp. 921–934, Sept. 1975.zbMATHCrossRefGoogle Scholar
  2. 2.
    S. Mita and Y. Ouchi, “A 150Mb/s PRML chip for magnetic disk drives,” in IEEE Inter. Solid-State Circuits Conference, San Francisco, CA, Feb. 1996, pp. 62–63.Google Scholar
  3. 3.
    G. T. Tuttle and G. D. Visshakhadatta, “A 130 Mb/s PRML read/write channel with digital-servo detection,” in IEEE Inter. Solid-State Circuits Conference, San Francisco, CA, Feb. 1996, pp. 64–65.Google Scholar
  4. 4.
    K. Parsi and N. Rao, “A 200 Mb/s PRML read/write channel IC,” in IEEE Inter. Solid-State Circuits Conference, San Francisco, CA, Feb. 1996, pp. 66–67.Google Scholar
  5. 5.
    R. R. Spencer, “Simulated performance of analog Viterbi detectors.” IEEE Journal on Selected Areas in Communications 10 (1), pp. 277–299, Jan. 1992.CrossRefGoogle Scholar
  6. 6.
    T. Roska and L. O. Chua, “The CNN universal machine: an analogic array machine.” IEEE Trans. on Circuits and Systems—II 40, pp. 163–173, Mar. 1993.MathSciNetzbMATHCrossRefGoogle Scholar
  7. 7.
    L. O. Chua and L. Yang, “Cellular neural networks: theory and applications.” IEEE Trans. on Circuits and Systems 35 (10), pp. 1257–1290, Oct. 1988.MathSciNetzbMATHCrossRefGoogle Scholar
  8. 8.
    A. Rodriguez, S. Espejo, R. Dominguez-Castro, J. Huertas, and E. Sanchez-Sinencio, “Current-mode techniques for implementation of continuous-and discrete-time cellular neural networks” IEEE Trans. on Circuits and Systems—II 40 (3), pp. 132–146, March 1993.zbMATHCrossRefGoogle Scholar
  9. 9.
    E. Y. Chou, B. J. Sheu, and R. H. Tsai, “A state constrained model for cellular non-linear network optimization,” accepted by IEEE Trans. on Circuits and Systems—I for publication.Google Scholar
  10. 10.
    H. Lin and D. Messerschmitt, “Parallel Viterbi decoding methods for uncontrollable and controllable sources.” IEEE Trans. on Communications 41, pp. 62–69, Jan. 1993.zbMATHCrossRefGoogle Scholar
  11. 11.
    G. Wade, Signal Coding and Processing. Cambridge University Press: New York, 1994.zbMATHCrossRefGoogle Scholar
  12. 12.
    S. H. Bang, B. J. Sheu, and E. Y. Chou, “A parallel hardware annealing method for optimal solutions of cellular neural networks.” IEEE Trans. on Circuits and Systems—II 43 (6), pp. 409–421, June 1996.CrossRefGoogle Scholar
  13. 13.
    G. D. Forney, Jr., “The Viterbi algorithm.” Proc. IEEE 61 (3), pp. 268–275, Mar. 1973.MathSciNetCrossRefGoogle Scholar
  14. 14.
    E. Franchi, M. Tartagni, R. Guerrieri, and G. Baccarani, “Random access analog memory for early vision.” IEEE Journal of Solid-State Circuits 27 (7), pp. 1105–1109, July 1992.CrossRefGoogle Scholar
  15. 15.
    HSPICE User’s Manual, Meta-software, Inc.: Campbell, CA, 1996.Google Scholar

Copyright information

© Springer Science+Business Media New York 1998

Authors and Affiliations

  • Michelle Yibing Wang
    • 1
  • Bing J. Sheu
    • 1
  • Theodore W. Berger
    • 2
  • Wayne C. Young
    • 1
  • Austin Kwang-Bo Cho
    • 1
  1. 1.Department of Electrical EngineeringUniversity of Southern CaliforniaLos AngelesUSA
  2. 2.Department of Biomedical EngineeringUniversity of Southern CaliforniaLos AngelesUSA

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