A 6 x 6 Cells Interconnection-Oriented Programmable Chip for CNN
The implementation of a versatile VLSI chip certainly represents an important step to improve the research on Cellular Neural Networks. In this paper a VLSI realization of the multi-chip oriented, the 6 × 6 Digitally Programmable Cellular Neural Network (6 × 6DPCNN) chip, will be presented. This chip covers most of the available one-neighbourhood templates for image processing applications. Moreover, it can be easily interconnected to others to carry out very large CNN arrays. The designs and some measured results of a single chip and a multi-chip board (the 720 DPCNN System) will be shown.
KeywordsInput Pattern Cellular Neural Network State Voltage Current Contribution VLSI Implementation
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