Global Design of Analog Cells Using Statistical Optimization Techniques

  • F. Medeiro
  • R. Rodríguez-Macías
  • F. V. Fernández
  • R. Domínguez-Castro
  • J. L. Huertas
  • A. Rodríguez-Vázquez


We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.


Design Objective Phase Margin Cool Schedule Global Design Integrate Circuit Design 
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Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • F. Medeiro
    • 1
  • R. Rodríguez-Macías
    • 1
  • F. V. Fernández
    • 1
  • R. Domínguez-Castro
    • 1
  • J. L. Huertas
    • 1
  • A. Rodríguez-Vázquez
    • 1
  1. 1.Dept. of Analog Circuit DesignCentro Nacional de Microelectrónica, Edificio CNMSevillaSpain

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