Advertisement

Global Design of Analog Cells Using Statistical Optimization Techniques

  • F. Medeiro
  • R. Rodríguez-Macías
  • F. V. Fernández
  • R. Domínguez-Castro
  • J. L. Huertas
  • A. Rodríguez-Vázquez
Chapter

Abstract

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.

Keywords

Design Objective Phase Margin Cool Schedule Global Design Integrate Circuit Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Degrauwe, M. G. R. et al., “IDAC: An interactive design tool for analog CMOS circuits,” IEEE Journal of Solid-State Circuits, Vol. 22, pp. 1106–1114, December 1987.CrossRefGoogle Scholar
  2. 2.
    Meixenberger, C., Henderson, R., Adder, L. and Degrauwe, M., “Tools for analog design,” Proc. Workshop on Advances in Analog Circuit Design, pp. 357–368, Scheveningen, The Netherlands, 1992.Google Scholar
  3. 3.
    El-Turky, E and Perry, E. E., “BLADES: An artificial intelligence approach to analog circuits design,” IEEE Trans. on Computer-Aided Design, Vol. 8, pp. 680–691, June 1989.CrossRefGoogle Scholar
  4. 4.
    Gielen, G. and Sansen, W., Symbolic Analysis for Automated Design of Analog Integrated Circuits. Kluwer, Boston, 1991.CrossRefGoogle Scholar
  5. 5.
    Haijani, R., Rutenbar, R. and Carley, L. R., “OASYS: A framework for analog circuits synthesis,” IEEE Trans. on Computer-Aided Design, Vol. 8, pp. 1247–1265, December 1989.CrossRefGoogle Scholar
  6. 6.
    Onodera, H. et al., “Operational-amplifier compilation with performance optimization,” IEEE Journal of Solid-State Circuits, Vol. 25, pp. 466 - j473, April 1990.CrossRefGoogle Scholar
  7. 7.
    Sheu, B. J., Lee, J. C. and Fung, A. H., “Flexible architecture approach to knowledge-based analogue IC design,” /EE Proceedings, Vol. 137, Pt. G, pp. 266–274, August 1990.Google Scholar
  8. 8.
    Young Koh, H., Sequin, C. H. and Gray, P. R., “OPASYN: A compiler for CMOS operational amplifier,” IEEE Trans. on Computer-Aided Design, Vol. 9, pp. 113–125, Feb. 1990.CrossRefGoogle Scholar
  9. 9.
    Gielen, G. E., Walsharts, H. and Sansen, W., “Analog circuits design optimization based on symbolic simulation and simulated annealing,” IEEE Journal of Solid-State Circuits, Vol. 25, pp. 707–713, June 1990.CrossRefGoogle Scholar
  10. 10.
    Makris, C. and Toumazou, C., “ISAID: Qualitative reasoning and trade-off analysis in analog IC design automation;” Proc. IEEE/nt. Symp. on Circuits and Systems, pp. 2364–2367, 1992.Google Scholar
  11. 11.
    Jongsma, J. et al., “An open design tool for analog circuits;” Proc. Int Symp. on Circuits and Systems, pp. 2000–2003, 1991.Google Scholar
  12. 12.
    Fernandez, F. V., Rodriguez-Vazquez, A. and Huertas, J. L., “Interactive AC modeling and characterization of analog circuits via symbolic analysis,” Analog Integrated Circuit and Signal Processing, Vol. 1, pp. 183–208, Kluwer, Nov. 1991.Google Scholar
  13. 13.
    Roser, B. E. and Wooley, B. A., “The design of sigma-delta modulation analog-to-digital converters,” IEEE Journal of Solid-State Circuits, Vol. 23, pp. 1298–1308, December 1988.CrossRefGoogle Scholar
  14. 14.
    Nye, W. et al., “DELIGHT.SPICE: An optimization-based system for the design of integrated circuits,” IEEE Trans. on Computer-Aided Design, Vol. 7, pp. 501–519, April 1988.CrossRefGoogle Scholar
  15. 15.
    Campbell, C. A., HSPICE User Manual. Meta Software Inc., 1988.Google Scholar
  16. 16.
    van Laarhoven, P. J. M. and Aatis, E. H. L., Simulated Annealing: Theory and Applications. Kluwer Academic Publishers, Boston, 1987.zbMATHCrossRefGoogle Scholar
  17. 17.
    Roberge, J. K., Operational Amplifiers: Theory and Practice. John Wiley & Sons Inc., New York, 1975.Google Scholar
  18. 18.
    Rutenbar, R. A., “Simulated annealing algorithms: An overview,” IEEE Circuits and Devices Magazine, Vol. 5, pp. 19–26, January 1989.CrossRefGoogle Scholar
  19. 19.
    Director, S., Maly, W. and Strojwas, A., VLSI Design for Manufacturing: Yield Enhancement. Kluwer Academic Publishers, Boston, 1990.CrossRefGoogle Scholar
  20. 20.
    Michael, C. and Ismail, M., “Statistical modeling of device mismatch for analog MOS integrated circuits,” IEEE Journal of Solid-State Circuits, Vol. 27, pp. 154–166, Feb. 1992.CrossRefGoogle Scholar
  21. 21.
    Pelgrom, M., Duinmaijer, A. and Welbers, A., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, Vol. 24, pp. 1433–1440, Oct. 1989.CrossRefGoogle Scholar
  22. 22.
    Wang, C., Castello, R. and Gray, P. R., “A scalable high-performance switched-capacitor filter,” IEEE Journal of Solid-State Circuits, Vol. 21, pp. 57–64, February 1986.CrossRefGoogle Scholar
  23. 23.
    Medeiro, F., Perez Verdu, B., Rodriguez-Vazquez, Y. and Huertas, J. L., “A tool for automated design of sigma-delta modulators using statistical optimization,” Proc. of ISCAS ’83, pp. 1373–1376. Chicago, May, 1993.Google Scholar

Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • F. Medeiro
    • 1
  • R. Rodríguez-Macías
    • 1
  • F. V. Fernández
    • 1
  • R. Domínguez-Castro
    • 1
  • J. L. Huertas
    • 1
  • A. Rodríguez-Vázquez
    • 1
  1. 1.Dept. of Analog Circuit DesignCentro Nacional de Microelectrónica, Edificio CNMSevillaSpain

Personalised recommendations