This work has addressed the problem of automatic layout generation for analog integrated circuits. In chapter 2 we have described the major layout parasitic effects that influence the performance of analog circuits: interconnect parasitics, device mismatch and thermal effects. All of these effects have to be taken into account simultaneously during layout in order to keep the performance degradation within specified limits. We have proposed a direct performance driven layout strategy that, when applied to the different layout steps, guarantees a fully functional layout that respects all performance constraints. The major novelty of the method is that it drives the layout tools directly by the performance constraints, without an intermediate parasitic constraint generation step. During placement and routing, the performance characteristics of the circuit are evaluated using a linear approximation based on performance sensitivities. Using this approach, a complete and sensible trade-off between different layout alternatives can be made on the fly, and the resulting circuit layout can be guaranteed to be correct.
KeywordsAnalog Circuit Performance Constraint Procedural Module Generator Layout Generation Circuit Layout
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