This chapter addresses the placement problem for high-performance analog circuits. The placement phase is crucial for the performance degradation of an analog circuit layout since it influences all the parasitic layout effects which have been discussed in chapter 2. The distance between matching devices, and therefore also their matching degree is determined during placement. The placement of a circuit also determines its thermal profile. In addition, it greatly influences the values of the interconnect parasitics. Although their final values are determined during routing, their minimum values are fixed by the configuration of the device terminals, which is determined during placement. A performance driven placement algorithm therefore has to take into account all of these performance degrading effects simultaneously.
KeywordsSimulated Annealing Discrete Cosine Transform Minimum Span Tree Simulated Annealing Algorithm Analog Circuit
Unable to display preview. Download preview PDF.