Performance Driven Layout of Analog Integrated Circuits
Generating the layout of high-performance analog circuits is a difficult and time-consuming task which has a considerable impact on circuit performance. The various parasitics which are introduced during the layout phase of an integrated circuit design can introduce intolerable performance degradation. Since these parasitics are unavoidable, the main concern in analog layout synthesis is to control the effects of the parasitics on cirçquit performance and to make sure that the circuit after layout still performs within its specifications.
KeywordsAnalog Circuit Parasitic Capacitance Adjoint Method Analog Integrate Circuit Power Supply Rejection Ratio
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