Performance Driven Layout of Analog Integrated Circuits

  • Koen Lampaert
  • Georges Gielen
  • Willy Sansen
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 501)

Abstract

Generating the layout of high-performance analog circuits is a difficult and time-consuming task which has a considerable impact on circuit performance. The various parasitics which are introduced during the layout phase of an integrated circuit design can introduce intolerable performance degradation. Since these parasitics are unavoidable, the main concern in analog layout synthesis is to control the effects of the parasitics on cirçquit performance and to make sure that the circuit after layout still performs within its specifications.

Keywords

Analog Circuit Parasitic Capacitance Adjoint Method Analog Integrate Circuit Power Supply Rejection Ratio 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1999

Authors and Affiliations

  • Koen Lampaert
    • 1
  • Georges Gielen
    • 1
  • Willy Sansen
    • 1
  1. 1.Katholieke Universiteit LeuvenBelgium

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