The Boundary-Scan standard

ANSI/IEEE Std 1149.1
  • Colin M. Maunder
  • Rodham E. Tulloss
Part of the Frontiers in Electronic Testing book series (FRET, volume 16)

Abstract

ANSI/IEEE Std 1149.1 defines a standard implementation of boundary-scan now built into many catalog and application-specific integrated circuits. The standard was developed as a solution to two continuing trends that are having a significant, adverse, impact on the task of testing loaded printed wiring boards: increasing chip complexity and greater miniaturization. The former increases the difficulty of test generation, while the latter impedes access for the bed-of-nails and hand-held probes on which many established test techniques depend.

Keywords

System Logic Controller State Current Instruction Instruction Register Bypass Register 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    ANSI/IEEE Std 1149.1 (revision b) — “Standard Test Access Port and Boundary-Scan Architecture”, IEEE,New York, 1994Google Scholar
  2. [2]
    C.M. Maunder and RE. Tulloss,“An Introduction to the Boundary-Scan Standard”, IEEE Computer Society Press,Los Alamitos, CA, 1990Google Scholar
  3. [3]
    B. Konemann et al.,“Built-in logic block observation techniques” Proceedings, International Test Conference,pp. 37–41, Los Alamitos, CA, 1979Google Scholar
  4. [4]
    Joint Electron Device Engineering Council,“Standard Manufacturer’s Identification Code” JEDEC Publication 106-A,July 1986. Obtainable from JEDEC, 2001 Eye Street NW, Washington DC 20006, USAGoogle Scholar
  5. [5]
    FPM Beenker,“Systematic and structured methods for digital board testing;” Proceedings, International Test Conference,pp. 380–385, 1985Google Scholar
  6. [6]
    C. W. Yau and N. Jarwala, “A new framework for analyzing test generation and diagnosis algorithms,” Proceedings, International Test Conference, pp. 63–70, 1989Google Scholar
  7. [7]
    N Jarwala and C. W. Yau,“A unified theory for designing optimal test generation and diagnosis algorithms for board interconnect”, Proceedings, International Test Conference,pp. 71–77, 1989Google Scholar
  8. [8]
    H.N. Scholz et al.,“ASIC implementations of boundary-scan and BIST,” Proceedings, 8th International Custom Microelectronics Conference,pp. 43.1–43.9, 1988Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Colin M. Maunder
    • 1
  • Rodham E. Tulloss
    • 2
  1. 1.British Telecom Advanced CommunicationsUK
  2. 2.RooseveltUSA

Personalised recommendations