Abstract
This chapter describes the VLSI implementation of a flexible motion estimation (ME) accelerator for low-power portable video real-time encoding applications. For low-power motion estimation the main design aim was to optimize the VLSI-architecture for low on-chip memory bandwidth, as the memory access bandwidth is directly related to power consumption. The second design goal was to take into account a low number of memory modules (or memory ports), cf. section 6.3.4. The presented VLSI architecture “Search Engine II”, [Kuhn 99], supports, besides the exhaustive search motion estimation, several ME algorithms with reduced computational complexity, in order to meet computational demands and power consumption requirements.
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Bibliography
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© 1999 Springer Science+Business Media Dordrecht
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Kuhn, P. (1999). VLSI Implementation: Search Engine II (1D Array). In: Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4474-3_8
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DOI: https://doi.org/10.1007/978-1-4757-4474-3_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5088-8
Online ISBN: 978-1-4757-4474-3
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