VLSI Implementation: Search Engine II (1D Array)

  • Peter Kuhn


This chapter describes the VLSI implementation of a flexible motion estimation (ME) accelerator for low-power portable video real-time encoding applications. For low-power motion estimation the main design aim was to optimize the VLSI-architecture for low on-chip memory bandwidth, as the memory access bandwidth is directly related to power consumption. The second design goal was to take into account a low number of memory modules (or memory ports), cf. section 6.3.4. The presented VLSI architecture “Search Engine II”, [Kuhn 99], supports, besides the exhaustive search motion estimation, several ME algorithms with reduced computational complexity, in order to meet computational demands and power consumption requirements.


Motion Estimation Clock Cycle Search Area Current Block VLSI Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Peter Kuhn
    • 1
  1. 1.Technical University of MunichGermany

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