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Design Space Motion Estimation Architectures

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Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

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Abstract

In this chapter motion estimation architectures are evaluated for the requirements of the visual (video) part of the MPEG-4 standard. Due to the very complex nature of the design space for motion estimation VLSI architectures, there are numerous VLSI architectures and design trade-offs. Proper consideration of these trade-offs can lead to an optimal VLSI architecture design for a selected motion estimation (ME) algorithm or a number of selected motion estimation algorithms under particular application constraints. The aim of this chapter is to evaluate block-matching motion estimation algorithms from a hardware point of view for MPEG-4. This is in contrast to the previous chapter where the block-matching algorithms were evaluated in terms of number of operations and memory bandwidth for software implementation on a programmable processor. It will be shown that the commonly used complexity metric of the number of operations for a processor implementation is not suitable for VLSI implementations.

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  1. Technical University of Munich, Germany

    Peter Kuhn

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© 1999 Springer Science+Business Media Dordrecht

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Kuhn, P. (1999). Design Space Motion Estimation Architectures. In: Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4474-3_6

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  • DOI: https://doi.org/10.1007/978-1-4757-4474-3_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5088-8

  • Online ISBN: 978-1-4757-4474-3

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