Synthesis of Reconfigurable Control Devices Based on Object-Oriented Specifications

  • Valery Sklyarov
  • António Adrego da Rocha
  • António Brito de Ferrari
Chapter

Abstract

There are many kinds of devices that can be decomposed into a datapath (execution unit) and control units. The datapath contains storage and functional units. A control unit performs a set of instructions by generating the appropriate sequence of microinstructions that depends on intermediate logic conditions or intermediate states of the datapath. Each instruction describes what operations must be applied to which operands stored in the datapath (or in external memory).

Keywords

Control Unit Field Programmable Gate Array Finite State Machine Control Circuit State Encode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [AtSi93]
    P. M. Athands, H. F. Silverman, “Processor Reconfiguration trough Instruction-Set Metamorphosis”, Computer, vol. 26, no 3, pp. 11–17, March, 1993.CrossRefGoogle Scholar
  2. [Bara94]
    S. Baranov, ”Logic Synthesis for Control Automata”. Kluwer Academic Publishers, 1994.Google Scholar
  3. [BaSk86]
    S. Baranov, V. Sklyarov, “Digital Devices Based on Programmable Matrix LSI”. Radio and Communications, Moscow, 1986.Google Scholar
  4. [Booc94]
    Grady Booch, “Object-Oriented Analysis and Design”, Second Edition, The Benjamin/Cummings Publishing Company, Inc., 1994.Google Scholar
  5. [Bost96]
    G.Bostock, “FPGAs and Programmable LSI. A designer’s handbook”. Butterworth-Heinemann, 1996.Google Scholar
  6. [Brow96]
    S.Brown, “FPGA Architectural Research: A Survey”,IEEE Design & Test of Computers, Vol. 13, No 4, pp 9–15, 1996.CrossRefGoogle Scholar
  7. [ChLe96]
    D.Chrepacha, D.Lewis, “DP-FPGA: An FPGA Architecture Optimized for Datapath”, VLSI Design, Vol. 4, No 4, pp. 329–343, 1996.CrossRefGoogle Scholar
  8. [ChLR93]
    Colin Charlton, Paul Leng, Mark Rivers, “An Object-Oriented Model of Design Evolution”, Microprocessing and Microprogramming, vol. 38, Numbers 1–5, pp. 441–448, September, 1993.Google Scholar
  9. [ELLV97]
    Stephen Edwards, Luciano Lavagno, Edward A.Lee, Alberto SangiovannyVincentelli, “Design of Embedded Systems: Formal Models, Validation, and Synthesis”, Proceeding of the IEEE, vol. 85, no. 3, pp. 366–390, March, 1997.CrossRefGoogle Scholar
  10. [Gokh91]
    M. Gokhale et al, “Building and Using a Highly-Parallel Programmable Logic Array”, Computer, vol. 24, no 1, pp. 81–89, January 1991.Google Scholar
  11. [Hura97]
    Laszio Huray, “Interoperable Objects for Distributed Real-Time Systems”, Embedded System Programming Europe, pp. 9–22, May, 1997.Google Scholar
  12. [IsSa93]
    C. Iseli, E. Sanchez, “Spyder: a Reconfigurable VLIW Processor Using FPGAs”, Proc. of the IEEE Workshop on FPGAs for Custom Computing Machines, pp. 17–24, April 1993.CrossRefGoogle Scholar
  13. [Katz94]
    Randy H. Katz, “Contemporary Logic Design”, The Benjamin/Cummings Publishing Company, Inc., 1994.Google Scholar
  14. [KiSk79]
    Victor Kirpichnikov, Valery Sklyarov, “Description and Synthesis of Control Devices”. USSR Academy of Science, Technical Cybernetics, N 1, pp 127–137, Moscow, 1979.Google Scholar
  15. [Kuma94]
    S.Kumar, J.H.Aylor, B.W.Johnson, W.A.Wulf, “Object-Oriented Techniques in Hardware Design”, Computer, vol. 27, no. 6, pp. 64–70, June, 1994.CrossRefGoogle Scholar
  16. [LySt96]
    Patric Lysaght, Jon Stockwood, “A Simulation Tool for Dynamically Reconfigurable Field Programmable Gate Arrays”, IEEE Trans. On VLSI Syst., vol. 4, no. 3, pp. 381–390, September, 1996.CrossRefGoogle Scholar
  17. [Mart95]
    Robert C. Martin, “Designing Object-Oriented C++ Applications Using the Booch Method”, Prentice Hall, 1995.Google Scholar
  18. [Maxf96]
    Maxfield, Clive “Max”, “Field Programmable Devices”, EDN, pp. 201–206, October 10, 1996.Google Scholar
  19. [Maye97]
    John H.Mayer, “Reconfigurable Computing Redefines Design Flexibility”,Computer Design, pp. 49–52, February, 1997.Google Scholar
  20. [Mich94]
    Giovanni De Micheli. “Synthesis and Optimization of Digital Circuits ”, McGraw-Hill, Inc., 1994.Google Scholar
  21. [Migu97]
    Giovanni de Micheli, Rajesh K. Gurta, “Hardware/Software Co-Design”, Proceeding of the IEEE, vol. 85, no. 3, pp. 349–365, March, 1997.CrossRefGoogle Scholar
  22. [Pirp97]
    Eric Pirpich, “Designing a more Flexible Programmable Logic Device - the XPLA”,Electronic Engineering, pp. 65–70, January, 1997.Google Scholar
  23. [RoS97a]
    António Adrego da Rocha, Valery Sklyarov, “VHDL Modeling of Hierarchical Finite State Machines”, Proceedings of the Fifth BELSIGN Workshop, Dresden, Germany, April, 1997.Google Scholar
  24. [RoS97b]
    Antonio Adrego da Rocha, Valery Sklyarov, “Simulação em VHDL de Máquinas de Estados Finitas Hierárquicas”, Electrónica e Telecomunicações, Vol 2, N 1, pp. 8394, 1997.Google Scholar
  25. [RoSF97]
    Antonio Adrego da Rocha, Valery Sklyarov, Antonio de Brito Ferrari. “Hierarchical Description and Design of Control Circuits Based on Reconfigurable and Reprogrammable Elements”, Proceeding of the International Workshop on Logic and Architectural Synthesis - IWLAS’97, Grenoble, December, 1997.Google Scholar
  26. [Sk182a]
    Valery Sklyarov, “Using Decoders in Control Units”, University News. Instruments, N 12, pp. 27–31, Leningrad (St.Petersburg), 1982.Google Scholar
  27. [Sk182b]
    Valery Sklyarov, “Synthesis of Control Units Based on Programmable Logic Devices”, USSR Academy of Science, Technical Cybernetics, N 5, pp. 59–69, Moscow, 1982.Google Scholar
  28. [Skl84a]
    V. Sklyarov, “Synthesis of Finite State Machines Based on Matrix LSI”, Science and Technique, Minsk, 1984.Google Scholar
  29. [Skl84b]
    Valery Sklyarov, “Hierarchical Graph-Schemes”, Latvian Academy of Science, Automatics and Computers, no. 2, pp. 82–87, Riga, 1984.Google Scholar
  30. [Sk1y87]
    Valery Sklyarov, “Parallel Graph-Schemes and Finite State Machines Synthesis”, Latvian Academy of Science, Automatics and Computers, no. 5, pp. 68–76, Riga, 1987.Google Scholar
  31. [Skly96]
    Valery Sklyarov, “Applying Finite State Machine Theory and Object-Oriented Programming to the Logical Synthesis of Control Devices”. Electrónica e Telecomunicações, 1996, Vol 1, N 6, pp. 515–529.Google Scholar
  32. [Skly97]
    Valery Sklyarov, “Understanding and Low Level Implementation Basic OOP Constructions”, Electrónica e Telecomunicações,Vol 1, N 7, pp. 729–738, 1997.Google Scholar
  33. [SkR96a]
    Valery Sklyarov, Antonio Adrego da Rocha, “Sintese de Unidades de Controlo Descritas por Grafos dum Esquema Hierarquicos”, Electrónica e Telecomunicações, vol. 1, no. 6, pp. 577–588, 1996.Google Scholar
  34. [SkR96b]
    Valery Sklyarov, António Adrego da Rocha, “Synthesis of Control Units Described by Hierarchical Graph-Schemes”, Proceedings of the Fourth BELSIGN Workshop, Santander, Spain, November, 1996.Google Scholar
  35. [SkRF97]
    Valery Sklyarov, Antonio Adrego da Rocha, Antonio de Brito Ferrari. “Applying Procedural and Object-Oriented Decomposition to the Logical Synthesis of Digital Devices”, Proceeding of the Second International Conference on Computer-Aided Design of Discrete Devices - CAD DD’97, Minsk, November, 1997.Google Scholar
  36. [VBRS96]
    Jean E.Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, Hervé H.Touati, Philippe Boucard, “Programmable Active Memories: Reconfigurable Systems Come of Age”, IEEE Trans. On VLSI Syst., vol. 4, no. 1, pp. 56–69, March, 1996.CrossRefGoogle Scholar
  37. [WRVr95]
    S.Wilton, J.Rose, Z.Vranesic, “Architecture of Centralized Field-Configurable Memory”, Proc. Third ACM Int’l Symp. On Field Programmable Gate Arrays, pp. 97103, Assoc. For Computing Machinery, New York, 1995.Google Scholar
  38. [Xi1i97]
    Xilinx, “XC6200 Field Programmable Gate Arrays”, Xilinx Product Description (Version 1.10), April 24, 1997.Google Scholar
  39. [ZhPa96]
    Wei Zhao, Christos A. Papachristou, “Synthesis of Reusable DSP Cores Based on Multiple Behaviour”, IEEE/ACM International Conference on Computer Aided Design, San Jose, California, pp. 103–108, November 10–14, 1996.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1998

Authors and Affiliations

  • Valery Sklyarov
  • António Adrego da Rocha
  • António Brito de Ferrari

There are no affiliations available

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