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Overlapped Scheduling Techniques for High-Level Synthesis and Multiprocessor Realizations of DSP Algorithms

  • Sabih H. Gerez
  • Sonia M. Heemstra de Groot
  • Erwin R. Bonsma
  • Marc J. M. Heijligers
Chapter

Abstract

Algorithms that contain computations that can be executed simultaneously, offer possibilities of exploiting the parallelism present by implementing them on appropriate hardware, such as a multiprocessor system or an application-specific integrated circuit (ASIC). Many digital signal processing (DSP) algorithms contain internal parallelism and are besides meant to be repeated infinitely (or a large number of times). These algorithms, therefore, not only have intra-iteration parallelism (between operations belonging to the same iteration) but inter-iteration parallelism (between operations belonging to different iterations) as well [Par91].

Keywords

Computational Node Interval Graph Delay Element Conflict Graph Target Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1998

Authors and Affiliations

  • Sabih H. Gerez
  • Sonia M. Heemstra de Groot
  • Erwin R. Bonsma
  • Marc J. M. Heijligers

There are no affiliations available

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