Abstract
In general three representations of a digital circuit or system can be distinguished,
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the structural at switch- or gate-level,
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the functional and
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the behavioral
on base of which, in accordance with an appropriate fault model, test patterns are generated. Hierarchical representations encompass two or more of these levels.
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References
Akers, S.B.: Functional Testing with Binary Decision Diagrams; Proc. 8 th Symp. Fault Tol. Comp., pp. 75–82, 1978.
Armstrong, J.R., Gray, F.G.,: Structured Logic Design with VHDL; Prentice-Hall, ISBN 0–13–885206–1, 1993.
Barclay, D.S., Armstrong, J.R.: A Heuristic Chip-Level Test Generation Algorithm; 23rd Design Automation Conference, pp. 257–262, 1986.
Barclay, D.S., Armstrong, J.R.: A Heuristic Chip-Level Test Generation Algorithm; 23rd Design Automation Conference, pp. 257–262, 1986.
Bashford, S., Bieker, U., Harking, B., Leupers, R., Marwedel, P., Neumann, A., Voggenauer, A., Voggenauer, D.: The MIMOLA language 4.1; University Dortmund, Informatik 12, 1994.
Bieker, U., Kaibel, M., Marwedel, P., Geisselhardt, W.: Hierarchical Test of Embedded Processors by Self-Test Programs
Bieker, U., Marwedel, P.: Retargetable self-test program generation using constraint logic programming; 32nd Design Automation Conference, 1995.
Bhattacharya, D., Murray, B.T., Hayes, J.P.: High-Level Test Generation for VLSI; IEEE Computer, pp. 16–24, 1989.
Brakel, G. van: Test Pattern Generation for Delay Faults; Doctoral Thesis, Universiteit Twente, Dept. Electr. Eng., 1995.
Chan, A.Y.: Easy-to-use Signature Analysis Accurately Troubleshoots Complex Logic Circuits; Hewlett-Packard Journal, Vol. 28, pp. 9–14, 1977.
Cho, C.H., Armstrong, J.R.: B-algorithm: A Behavioral Test Generation Algorithm; Proc. ITC, pp.. 968–979, 1994.
Cheng, W.: The Back Algorithm for Sequential Test Generation; Proceedings International Conference on Computer Design, pp. 66–69, 1988.
Cheng, W., Patel, J.H.: PROOFS: A Super Fault Simulator for Sequential Circuits; Proc. Europ. Design Autom. Conf., pp. 475–479, 1990.
Emshoff, B., Kaibel, M.: Einfuehrung Binaerer Entscheidungsgraphen auf hoher Beschreibungsebene in VHDL; Proc. in German 7. EIS Workshop,pp. 129–132, 1995.
Gouders, N., Kaibel, R.: Advanced Techniques for Sequential Test Generation; Proc. ETC, pp. 293–300, 1991.
Gouders, N., Kaibel, R.: PARIS: A parallel pattern fault simulator for synchronous sequential circuits; Proc. ICCD, pp. 542–545, 1991.
Gläser, U.: Mehrebenen - Testgenerierung für Synchrone Schaltwerke; Doctoral Thesis in German, Univ. Duisburg, Electrical Eng. Dept., 1994.
Geisselhardt, W., Mojtahedi, M.: New methods for parallel pattern fast fault simulation for synchronous sequential circuits. Proc. ICCAD, 1993.
Geisselhardt, W., Mohrs, W., Moeller, U.: FUNTEST–Functional Test generation for VLSI-Circuits and Systems; Microelectronic Reliability, Vol. 29, No. 3, pp. 357–364, 1989.
Gouders, N.: Methoden zur deterministischen Testgenerierung fir synchrone Schaltwerke; Doctoral Thesis in German, Univ. Duisburg, Electrical Eng. Dept., 1991.
Goel, P.: An implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits; IEEE Trans. Comp., Vol. C-30, pp. 215–222, March 1981.
Giambiasi, N., Santucci, J.F., Courbis, A.L., Pla, V.: Test Pattern Generation for Behavioral Descriptions in VHDL; Proc. EuroVHDL’91, Stockholm, pp. 228–235, 1991.
Gulbins, M., Straube, B.: Applying Behavioral Level Test Generation to High-Level Design Validation, Proc. of EDandTC, pp. 613, 1996
Hassan, S.Z., Lu, D.J., McCluskey, E.J.: Parallel Signature Analyzers–Detection Capability and Extensions; 26 th; IEEE COMPCON, pp. 440–445, 1983.
Hennie, F.C.: Finite-State Models for Logical Machines John Wiley and Sons, 1968
Huemmer, H.-D., Veit, H., Toepfer, H.: Functional Tests for Hardware Derived from VHDL Description; Proc. CHDL, pp. 433–445, 1991
Design Automation Standards Subcommittee of the IEEE: Draft standard VHDL language reference manual; IEEE Standards Department, 1992.
Johnson, W.A.: Behavioral-Level Test Development; Proceedings 16th Design Automation Conference, pp. 171–179, 1979.
Kaibel, M., Emshoff, B., Geisselhardt, W.: Investigations on High-Level Control for Gate-Level ATPG, Proc. European Test Workshop, Montpellier, pp. 192–201, 1996.
Levendel, Y.H., Menon, P.R.: Test Generation Algorithms for Computer Hardware Description Languages; IEEE Trans. on Computers, Vol. C-31, No. 7, pp. 577–588, 1982.
Lee, J., Patel, J.H.: An Architectural Level Test Generator for a Hierarchical Design Environment; Proc. 21 th Symp. on Fault-Tolerant Comp., pp. 44–51, 1991.
Lin, T.: The S-Algorithm: A Promising Solution for Systematic Functional Test Generation; Proc. Int. Conference on Computer-Aided Design, pp. 134–136, 1984.
Marwedel, P., Goossens, G. editors: Code Generation for Embedded Processors; Kluwer Academic Publishers, 1995.
Mojtahedi, M.: Methoden zur Beschleunigung der automatischen Testmustergenerierung und Fehlersimulation für synchrone sequentielle Schaltungen; Doctoral Thesis in German, Univ. Duisburg, Electrical Eng. Dept., 1994.
Myers, G.J.: The Art of Software Testing; John Wiley and Sons, 1979.
O’Neill, M.D., Jani, D.D., Cho, C.H., Armstrong, J.R.: BTG: A Behavioral Test Generator; Proc. CHDL, pp. 347–361, 1989.
O’Neill, M.D., Jani, D.D., Cho, C.H., Armstrong, J.R.: BTG: A Behavioral Test Generator; Proc. CHDL, pp. 347–361, 1990.
Roth, J.P.: Diagnosis of Automata Failures. A Calculus and a Model; IBM Jounal of Research and Development, V. 9, No. 2, 1966.
Sarfert, T.M., Markgraf, R., Trischler, E., Schulz, M.H.: Hierarchical Test Pattern Generation Based on High-Level Primitives; Proc. IEEE Int. Test Conf., pp. 1016–1026, Sept. 1989.
SPARC International Inc.: The SPARC Architecture Manual; Version 8, Prentice Hall, 1992
Veit, H.H.: A Contribution to the Generation of Tests for Digital Circuits Described by Their Behavior; Doctoral Thesis, Univ. Duisburg, Electrical Eng. Dept., 1992
Vishakantaiah, P., Abraham, J., Abadir, M.: Automatic Test Knowledge Extraction from VHDL (ATKET); 29th ACM/IEEE Design Automation Conference, pp. 273–278, 1992.
Huemmer, H.-D., Wiemers, T., Geisselhardt, W., Splettstoesser, W.: TAMUX: Test Access via Multiplexers with minimum area overhead and at speed testability; 3rd International Test Synthesis Workshop, Sta. Barbara, CA, May 6–8, 1996
Williams, T.W., Parker, K.S.: Design for Testability: a Survey; IEEE Trans. Comp., Vol. C-13, No. 1, pp. 2–15, 1982.
Yount, Ch.R., Siewiorek, D. P.: A Methodology for the Rapid Injection of Transient HardwareErrors; IEEE Trans. on Comp., No. 8, pp. 881–891, 1996.
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Geisselhardt, W., Huemmer, HD. (1998). Advances in ATPG by Exploiting the Behavioral View. In: López, J.C., Hermida, R., Geisselhardt, W. (eds) Advanced Techniques for Embedded Systems Design and Test. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4419-4_10
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