Abstract
Minimizing the total routed wirelength is one of the fundamental goals in VLSI placement stage. In order to achieve such a challenging objective, a number of heuristics and objective functions were proposed in the past couple of decades. Half-perimeter wirelength has emerged as the most typical objective in placement because it adequately models the routed wirelength, especially for two-terminal and three-terminal nets. In general, it is believed that there is a positive correlation between halfperimeter wirelength and routed wirelength. Many successful placement tools are based on half-perimeter wirelength minimization [134, 139].
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Notes
Accurate available routing resources can only be obtained after placement and global routing with the consideration of the layer area occupied by placed cells and the number of routing layers. However a main portion of routing resources could be predicted at this point.
A tile has unit width and height.
We assume that the global routing tiles are square.
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© 2003 Springer Science+Business Media New York
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Sarrafzadeh, M., Wang, M., Yang, X. (2003). Congestion Estimation. In: Modern Placement Techniques. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3781-3_4
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DOI: https://doi.org/10.1007/978-1-4757-3781-3_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5309-4
Online ISBN: 978-1-4757-3781-3
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